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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonint8x16_tvsraq_n_s8(int8x16_t a, int8x16_t b, const int n)Shift / Right / Vector shift right and accumulate
Description
Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.
Results
Vd.16B result
This intrinsic compiles to the following instructions:

SSRA Vd.16B,Vn.16B,#n

Argument Preparation
a register: Vd.16Bb register: Vn.16Bn minimum: 1; maximum: 8
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand  = V[n];
bits(datasize) operand2;
bits(datasize) result;
integer round_const = if round then (1 << (shift - 1)) else 0;
integer element;

operand2 = if accumulate then V[d] else Zeros();
for e = 0 to elements-1
    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

V[d] = result;