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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonpoly64x1_tvsri_n_p64(poly64x1_t a, poly64x1_t b, const int n)Shift / Right / Vector shift right and insert
Description
Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.
Results
Dd result
This intrinsic compiles to the following instructions:

SRI Dd,Dn,#n

Argument Preparation
a register: Ddb register: Dnn minimum: 1; maximum: 64
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand  = V[n];
bits(datasize) operand2 = V[d];
bits(datasize) result;
bits(esize) mask = LSR(Ones(esize), shift);
bits(esize) shifted;

for e = 0 to elements-1
    shifted = LSR(Elem[operand, e, esize], shift);
    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
V[d] = result;