Search all intrinsics
SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint16x4_tvsri_n_u16(uint16x4_t a, uint16x4_t b, const int n)Shift / Right / Vector shift right and insert
Description
Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.
Results
Vd.4H result
This intrinsic compiles to the following instructions:

SRI Vd.4H,Vn.4H,#n

Argument Preparation
a register: Vd.4Hb register: Vn.4Hn minimum: 1; maximum: 16
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand  = V[n];
bits(datasize) operand2 = V[d];
bits(datasize) result;
bits(esize) mask = LSR(Ones(esize), shift);
bits(esize) shifted;

for e = 0 to elements-1
    shifted = LSR(Elem[operand, e, esize], shift);
    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
V[d] = result;