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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint8x8_tvtrn1_u8(uint8x8_t a, uint8x8_t b)Vector manipulation / Transpose elements
Description
Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.
Results
Vd.8B result
This intrinsic compiles to the following instructions:

TRN1 Vd.8B,Vn.8B,Vm.8B

Argument Preparation
a register: Vn.8Bb register: Vm.8B
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];

V[d] = result;