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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint32x4_tvtrn1q_u32(uint32x4_t a, uint32x4_t b)Vector manipulation / Transpose elements
Description
Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.
Results
Vd.4S result
This intrinsic compiles to the following instructions:

TRN1 Vd.4S,Vn.4S,Vm.4S

Argument Preparation
a register: Vn.4Sb register: Vm.4S
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];

V[d] = result;