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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint64x2_tvtstq_p64(poly64x2_t a, poly64x2_t b)Compare / Bitwise not equal to zero
Description
Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.
Results
Vd.2D result
This intrinsic compiles to the following instructions:

CMTST Vd.2D,Vn.2D,Vm.2D

Argument Preparation
a register: Vn.2Db register: Vm.2D
Architectures
A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
boolean test_passed;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if and_test then
        test_passed = !IsZero(element1 AND element2);
    else
        test_passed = (element1 == element2);
    Elem[result, e, esize] = if test_passed then Ones() else Zeros();

V[d] = result;