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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint16x8_tvzip1q_u16(uint16x8_t a, uint16x8_t b)Vector manipulation / Zip elements
Description
Zip vectors (primary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.
Results
Vd.8H result
This intrinsic compiles to the following instructions:

ZIP1 Vd.8H,Vn.8H,Vm.8H

Argument Preparation
a register: Vn.8Hb register: Vm.8H
Architectures
A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

integer base = part * pairs;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

V[d] = result;