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SIMD ISAReturn TypeNameArgumentsInstruction Group
Neonuint16x4x2_tvzip_u16(uint16x4_t a, uint16x4_t b)Vector manipulation / Zip elements
Description
Interleave two vectors. This intrinsic reads corresponding elements from the two source vectors as pairs, interleaves the pairs, and returns the resulting interleaved vector.
Results
Vd1.4H result.val[0]Vd2.4H result.val[1]
This intrinsic compiles to the following instructions:

ZIP1 Vd1.4H,Vn.4H,Vm.4H

ZIP2 Vd2.4H,Vn.4H,Vm.4H

Argument Preparation
a register: Vn.4Hb register: Vm.4H
Architectures
v7, A32, A64

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;

integer base = part * pairs;

for p = 0 to pairs-1
    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

V[d] = result;