MVE Intrinsics

Arm Helium technology is the M-Profile Vector Extension (MVE) for the Arm Cortex-M processor series. 

MVE intrinsics are function calls that the compiler replaces with an appropriate MVE instruction or sequence of MVE instructions. Intrinsics provide almost as much control as writing assembly language, but leave the allocation of registers to the compiler, so that developers can focus on the algorithms. It can also perform instruction scheduling to remove pipeline stalls for the specified target processor. This leads to more maintainable source code than using assembly language. MVE intrinsics are supported by Arm Compilers, gcc and LLVM.

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.

For more information about the concepts and usage related to the MVE intrinsics, see the Arm C Language Extensions documentation.

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Return a vector where its register representation is the same as the concatenation of the two 64-bit values.

T32 Instruction

VMOV Qd[2], Qd[0], Rt3, Rt
VMOV Qd[3], Qd[1], Rt4, Rt2

Argument Preparation

a → [Rt,  Rt2] 
b → [Rt3, Rt4]

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U8 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U16 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U32 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U8 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U16 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDDUP.U32 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U8 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U16 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U32 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U8 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U16 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDDUPT.U32 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U8 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U16 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U32 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U8 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U16 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VDWDUP.U32 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U8 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U16 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U32 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U8 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U16 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively decrementing values, starting at an offset specified by Rn. The value is decremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the decrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VDWDUPT.U32 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U8 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U16 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U32 Qd, Rn, imm

Argument Preparation

a → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U8 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U16 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIDUP.U32 Qd, Rn, imm

Argument Preparation

*a → Rn 

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U8 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U16 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U32 Qd, Rn, imm

Argument Preparation

inactive → Qd 
a → Rn
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U8 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U16 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIDUPT.U32 Qd, Rn, imm

Argument Preparation

inactive → Qd 
*a → Rn
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U8 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U16 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U32 Qd, Rn, Rm, imm

Argument Preparation

a → Rn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U8 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U16 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VIWDUP.U32 Qd, Rn, Rm, imm

Argument Preparation

*a → Rn 
b → Rm

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U8 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U16 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U32 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
a → Rn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U8 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U16 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Creates a vector with elements of successively incrementing values, starting at an offset specified by Rn. The value is incremented by the specified immediate value, which can take the following values: 1, 2, 4, 8. For the wrapping variant, if Rn and Rm are not a multiple of imm, or if Rn >= Rm, the operation is CONSTRAINED UNPREDICTABLE, with the resulting values of Rn and Qd UNKNOWN, otherwise the operation wraps so that the values written to the vector register elements are in the range [0, Rm). If Rn and Rm are not a multiple of imm, the incrementing value will not wrap. In all cases, the updated start offset is written back to Rn.

T32 Instruction

VMSR P0, Rp
VPST
VIWDUPT.U32 Qd, Rn, Rm, imm

Argument Preparation

inactive → Qd 
*a → Rn
b → Rm
p → Rp

Result

Qd → result
Rn → *a

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.8 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.16 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.32 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.8 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.16 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.32 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.16 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VDUP.32 Qd, Rt

Argument Preparation

a → Rt 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.8 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.16 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.32 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.8 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.16 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.32 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.16 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Set each element of a vector register to the value of a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VDUPT.32 Qd, Rt

Argument Preparation

inactive → Qd 
a → Rt
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 eq, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 eq, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 ne, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I8 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.I32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I8 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I16 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.I32 ne, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 ge, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 ge, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 gt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 gt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 le, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 le, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 lt, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F16 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.F32 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S8 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S16 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.S32 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F16 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.F32 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S8 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S16 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.S32 lt, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U8 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U16 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U32 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U8 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U16 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U32 cs, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U8 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U16 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U32 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U8 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U16 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U32 cs, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U8 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U16 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U32 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U8 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U16 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U32 hi, Qn, Qm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Qm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U8 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U16 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VCMP.U32 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U8 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U16 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Perform a lane-wise comparison between each element in the first source vector register and either the respective elements in the second source vector register or the value of a general-purpose register. The resulting boolean conditions are placed in VPR.P0. The VPR.P0 flags for predicated lanes are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VCMPT.U32 hi, Qn, Rm
VMRS Rd, P0

Argument Preparation

a → Qn 
b → Rm
p → Rp

Result

Rd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMIN.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINA.S8 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINA.S16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINA.S32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINAT.S8 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINAT.S16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINAT.S32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.U8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.U16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINV.U32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.U8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.U16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINVT.U32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINAV.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINAV.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMINAV.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINAVT.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINAVT.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMINAVT.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINNM.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINNM.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINNMA.F16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMINNMA.F32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMAT.F16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point minimum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The smaller values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMAT.F32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMINNMV.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMINNMV.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMVT.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMVT.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMINNMAV.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMINNMAV.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMAVT.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the minimum value of the elements in a vector register. Store the minimum value in the general-purpose destination register only if it is smaller than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMINNMAVT.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAX.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXA.S8 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXA.S16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXA.S32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAT.S8 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAT.S16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in the source operands, and store the result in the corresponding destination elements. The absolute variant takes the elements from the destination vector, treating them as unsigned, and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAT.S32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.U8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.U16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXV.U32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.U8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.U16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXVT.U32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXAV.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXAV.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMAXAV.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAVT.S8 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAVT.S16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. The result of the operation is sign-extended to 32 bits before being stored back. The absolute variant of the instruction compares the absolute value of signed vector elements and treats the value in the general-purpose register as unsigned.

T32 Instruction

VMSR P0, Rp
VPST
VMAXAVT.S32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXNM.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXNM.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXNMA.F16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMAXNMA.F32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMAT.F16 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the floating-point maximum number of the elements in the source operands, and store the result in the corresponding destination elements. It handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant takes the absolute values of the elements from the destination vector and compares them to the absolute values of the corresponding elements in the source vector. The larger values are stored back into the destination vector.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMAT.F32 Qda, Qm

Argument Preparation

a → Qda 
b → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMAXNMV.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMAXNMV.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMVT.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMVT.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMAXNMAV.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMAXNMAV.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMAVT.F16 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Find the maximum value of the elements in a vector register. Store the maximum value in the general-purpose destination register only if it is larger than the starting value of the general-purpose destination register. The general-purpose register is read as the same width as the vector elements. For half-precision the upper half of the general-purpose register is cleared on writeback. This instruction handles NaNs in consistence with the IEEE754-2008 specification, and returns the numerical operand when one operand is numerical and the other is a quiet NaN. The absolute variant of the instruction compares the absolute value of vector elements.

T32 Instruction

VMSR P0, Rp
VPST
VMAXNMAVT.F32 Rda, Qm

Argument Preparation

a → Rda 
b → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.S8 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.S16 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.S32 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.U8 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.U16 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VABAV.U32 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.S8 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.S16 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.S32 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.U8 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.U16 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector and accumulate the absolute values of the results. The initial value of the general-purpose destination register is added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VABAVT.U32 Rda, Qn, Qm

Argument Preparation

a → Rda 
b → Qn
c → Qm
p → Rp

Result

Rda → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VABD.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the elements of the second source vector register from the corresponding elements of the first source vector register and place the absolute values of the results in the elements of the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABDT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VABS.F16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VABS.F32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VABS.S8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VABS.S16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VABS.S32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABST.F16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABST.F32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABST.S8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABST.S16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VABST.S32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VADCI.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VADCI.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VADCIT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VADCIT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VADC.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm
*carry → Rt

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VADC.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm
*carry → Rt

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VMSR P0, Rp
VPST
VADCT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
*carry → Rt
p → Rp

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Add with carry across beats, with carry in from and out to FPSCR.C. Initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled because of predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VMSR P0, Rp
VPST
VADCT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
*carry → Rt
p → Rp

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VADD.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VADD.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.F16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.F32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VADD.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VADD.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.F16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.F32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add across the elements of a vector accumulating the result into a scalar. The initial value of the general-purpose destination register can optionally be added to the result.

T32 Instruction

VMSR P0, Rp
VPST
VADDT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VCLS.S8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VCLS.S16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VCLS.S32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLST.S8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLST.S16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading sign bits of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLST.S32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VCLZ.I32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Count the leading zeros of each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCLZT.I32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value of each element of a vector register.

T32 Instruction

VNEG.F16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value of each element of a vector register.

T32 Instruction

VNEG.F32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value of each element of a vector register.

T32 Instruction

VNEG.S8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value of each element of a vector register.

T32 Instruction

VNEG.S16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value of each element of a vector register.

T32 Instruction

VNEG.S32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VNEGT.F16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VNEGT.F32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VNEGT.S8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VNEGT.S16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value of each element of a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VNEGT.S32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMULH.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in a vector register by its respective element in another vector register and return the high half of the result. The result is optionally rounded before the high half is selected.

T32 Instruction

VMSR P0, Rp
VPST
VMULHT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.P8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.P16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLB.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.P8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.P16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLBT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.P8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.P16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMULLT.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.P8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise polynomial multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.P16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements. The operation produces a double-width result.

T32 Instruction

VMSR P0, Rp
VPST
VMULLTT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.F16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.F32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMUL.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.F16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.F32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply the value of the elements in the first source vector register by either the respective elements in the second source vector register or a general-purpose register.

T32 Instruction

VMSR P0, Rp
VPST
VMULT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VSBCI.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VSBCI.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VSBCIT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMSR P0, Rp
VPST
VSBCIT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result
Rt → *carry_out

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VSBC.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm
*carry → Rt

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VSBC.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

a → Qn 
b → Qm
*carry → Rt

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VMSR P0, Rp
VPST
VSBCT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
*carry → Rt
p → Rp

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Beat-wise subtracts the value of the elements in the second source vector register and the value of NOT(Carry flag) from the respective elements in the first source vector register, the carry flag being FPSCR.C. The initial value of FPSCR.C can be overridden by using the I variant. Note: FPSCR.C is not updated for beats disabled due to predication. FPSCR.N, .V and .Z are zeroed.

T32 Instruction

VMRS Rs, FPSCR_nzcvqc
BFI Rs, Rt, #29, #1
VMSR FPSCR_nzcvqc, Rs
VMSR P0, Rp
VPST
VSBCT.I32 Qd, Qn, Qm
VMRS Rt, FPSCR_nzcvqc
LSR Rt, #29
AND Rt, #1

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
*carry → Rt
p → Rp

Result

Qd → result
Rt → *carry

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.I32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.F16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.F32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.F16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VSUB.F32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.I32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.F16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.F32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.F16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is then written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VSUBT.F32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.F16 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.F32 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I8 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I16 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I32 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I8 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I16 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I32 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.F16 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.F32 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I8 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I16 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I32 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I8 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I16 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VCADD.I32 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.F16 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.F32 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I8 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I16 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I32 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I8 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I16 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I32 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.F16 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.F32 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I8 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I16 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I32 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I8 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I16 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction performs a complex addition of the first operand with the second operand rotated in the complex plane by the specified amount. A 90 degree rotation of this operand corresponds to a multiplication by a positive imaginary unit, while a 270 degree rotation corresponds to a multiplication by a negative imaginary unit. Even and odd elements of the source vectors are interpreted to be the real and imaginary components, respectively, of a complex number. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCADDT.I32 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F16 Qda, Qn, Qm, #0

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F32 Qda, Qn, Qm, #0

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F16 Qda, Qn, Qm, #90

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F32 Qda, Qn, Qm, #90

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F16 Qda, Qn, Qm, #180

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F32 Qda, Qn, Qm, #180

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F16 Qda, Qn, Qm, #270

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VCMLA.F32 Qda, Qn, Qm, #270

Argument Preparation

a → Qda 
b → Qn
c → Qm

Result

Qda → result

Supported architectures

MVE/NEON

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F16 Qda, Qn, Qm, #0

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F32 Qda, Qn, Qm, #0

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F16 Qda, Qn, Qm, #90

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F32 Qda, Qn, Qm, #90

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F16 Qda, Qn, Qm, #180

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F32 Qda, Qn, Qm, #180

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F16 Qda, Qn, Qm, #270

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The result of the multiplication is added on to the existing value in the destination vector register. The multiplication and addition operations are fused and the result is not rounded.

T32 Instruction

VMSR P0, Rp
VPST
VCMLAT.F32 Qda, Qn, Qm, #270

Argument Preparation

a → Qda 
b → Qn
c → Qm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F16 Qd, Qn, Qm, #0

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F32 Qd, Qn, Qm, #0

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F16 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F32 Qd, Qn, Qm, #90

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F16 Qd, Qn, Qm, #180

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F32 Qd, Qn, Qm, #180

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F16 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VCMUL.F32 Qd, Qn, Qm, #270

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F16 Qd, Qn, Qm, #0

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F32 Qd, Qn, Qm, #0

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F16 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F32 Qd, Qn, Qm, #90

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F16 Qd, Qn, Qm, #180

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F32 Qd, Qn, Qm, #180

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F16 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

This instruction operates on complex numbers that are represented in registers as pairs of elements. Each element holds a floating-point value. The odd element holds the imaginary part of the number, and the even element holds the real part of the number. The instruction performs the computation on the corresponding complex number element pairs from the two source registers and the destination register. Considering the complex number from the second source register on an Argand diagram, the number is rotated counterclockwise by 0, 90, 180, or 270 degrees. If the transformation was a rotation by 0 or 180 degrees, the two elements of the transformed complex number are multiplied by the real element of the first source register. If the transformation was a rotation by 90 or 270 degrees, the two elements are multiplied by the imaginary element of the complex number from the first source register. The results are written into the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VCMULT.F32 Qd, Qn, Qm, #270

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VQABS.S8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VQABS.S16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VQABS.S32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQABST.S8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQABST.S16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Compute the absolute value of and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQABST.S32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQADD.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Add the value of the elements in the first source vector register to either the respective elements in the second source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQADDT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADH.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADH.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADH.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADHX.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADHX.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLADHX.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHXT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHXT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLADHXT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADH.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADH.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADH.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADHX.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADHX.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLADHX.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHXT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHXT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by adding them together and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLADHXT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLAH.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLAHT.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLAH.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by a scalar value, double the result and add to the respective element from the destination vector High Half. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLAHT.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLASH.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.S8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.S16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.S32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.U8 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.U16 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

Multiply each element in the source vector by the respective element from the destination vector, double the result and add to a scalar value. Store the high half of each result in the destination register. The result is optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLASHT.U32 Qda, Qn, Rm

Argument Preparation

a → Qda 
b → Qn
c → Rm
p → Rp

Result

Qda → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDH.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDH.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDH.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDHX.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDHX.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQDMLSDHX.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHXT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHXT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMLSDHXT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDH.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDH.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDH.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDHX.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDHX.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VQRDMLSDHX.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHXT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHXT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

The elements of the vector registers are handled in pairs. In the base variant, corresponding elements from the two source registers are multiplied together, whereas the exchange variant swaps the values in each pair of values read from the first source register, before multiplying them with the values from the second source register. The results of the pairs of multiply operations are combined by subtracting one from the other and doubling the result. The high halves of the resulting values are selected as the final results. The base variant writes the results into the lower element of each pair of elements in the destination register, whereas the exchange variant writes to the upper element in each pair. The results are optionally rounded before the high half is selected and saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMLSDHXT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQDMULH.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VQRDMULH.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Multiply a general-purpose register value by each element of a vector register to produce a vector of results or multiply each element of a vector register by its corresponding element in another vector register, double the results, and place the most significant half of the final results in the destination vector. The results are optionally rounded before being saturated.

T32 Instruction

VMSR P0, Rp
VPST
VQRDMULHT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLB.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLB.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLBT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLBT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLB.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLB.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLBT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLBT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLT.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLT.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLTT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLTT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLT.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VQDMULLT.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLTT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Performs an element-wise integer multiplication of two single-width source operand elements. These are selected from either the top half (T variant) or bottom half (B variant) of double-width source vector register elements or the lower single-width portion of the general-purpose register. The product of the multiplication is doubled and saturated to produce a double-width product that is written back to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQDMULLTT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VQNEG.S8 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VQNEG.S16 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VQNEG.S32 Qd, Qm

Argument Preparation

a → Qm 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQNEGT.S8 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQNEGT.S16 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Negate the value and saturate each element in a vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQNEGT.S32 Qd, Qm

Argument Preparation

inactive → Qd 
a → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U8 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U16 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U32 Qd, Qn, Rm

Argument Preparation

a → Qn 
b → Rm

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U8 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U16 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U32 Qd, Qn, Rm

Argument Preparation

inactive → Qd 
a → Qn
b → Rm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.S32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U8 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U16 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VQSUB.U32 Qd, Qn, Qm

Argument Preparation

a → Qn 
b → Qm

Result

Qd → result

Supported architectures

MVE/NEON

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.S32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U8 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U16 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Subtract the value of the elements in the second source vector register from either the respective elements in the first source vector register or a general-purpose register. The result is saturated before being written to the destination vector register.

T32 Instruction

VMSR P0, Rp
VPST
VQSUBT.U32 Qd, Qn, Qm

Argument Preparation

inactive → Qd 
a → Qn
b → Qm
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.8 {Qd - Qd2}, [Rn]
VLD21.8 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.16 {Qd - Qd2}, [Rn]
VLD21.16 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.32 {Qd - Qd2}, [Rn]
VLD21.32 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.8 {Qd - Qd2}, [Rn]
VLD21.8 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.16 {Qd - Qd2}, [Rn]
VLD21.16 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.32 {Qd - Qd2}, [Rn]
VLD21.32 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.16 {Qd - Qd2}, [Rn]
VLD21.16 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 2 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 2 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 2. The base address register can optionally be incremented by 32.

T32 Instruction

VLD20.32 {Qd - Qd2}, [Rn]
VLD21.32 {Qd - Qd2}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.8 {Qd - Qd4}, [Rn]
VLD41.8 {Qd - Qd4}, [Rn]
VLD42.8 {Qd - Qd4}, [Rn]
VLD43.8 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.16 {Qd - Qd4}, [Rn]
VLD41.16 {Qd - Qd4}, [Rn]
VLD42.16 {Qd - Qd4}, [Rn]
VLD43.16 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.32 {Qd - Qd4}, [Rn]
VLD41.32 {Qd - Qd4}, [Rn]
VLD42.32 {Qd - Qd4}, [Rn]
VLD43.32 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.8 {Qd - Qd4}, [Rn]
VLD41.8 {Qd - Qd4}, [Rn]
VLD42.8 {Qd - Qd4}, [Rn]
VLD43.8 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.16 {Qd - Qd4}, [Rn]
VLD41.16 {Qd - Qd4}, [Rn]
VLD42.16 {Qd - Qd4}, [Rn]
VLD43.16 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.32 {Qd - Qd4}, [Rn]
VLD41.32 {Qd - Qd4}, [Rn]
VLD42.32 {Qd - Qd4}, [Rn]
VLD43.32 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.16 {Qd - Qd4}, [Rn]
VLD41.16 {Qd - Qd4}, [Rn]
VLD42.16 {Qd - Qd4}, [Rn]
VLD43.16 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Loads two 64-bit contiguous blocks of data from memory and writes them to parts of 4 destination registers. The parts of the destination registers written to, and the offsets from the base address register, are determined by the "pat" parameter. If the instruction is executed 4 times with the same base address and destination registers, but with different "pat" values, the effect is to load data from memory and to deinterleave it into the specified registers with a stride of 4. The base address register can optionally be incremented by 64.

T32 Instruction

VLD40.32 {Qd - Qd4}, [Rn]
VLD41.32 {Qd - Qd4}, [Rn]
VLD42.32 {Qd - Qd4}, [Rn]
VLD43.32 {Qd - Qd4}, [Rn]

Argument Preparation

addr → Rn 

Result

Qd → result.val[0]
Qd2 → result.val[1]
Qd3 → result.val[2]
Qd4 → result.val[3]

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.8 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.S16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.S32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.8 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.U16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.U32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.8 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.S16 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.S32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.8 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.U16 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRBT.U32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.S32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.U32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRHT.S16 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRHT.S32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRHT.U16 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRHT.U32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRHT.F16 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRWT.32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRWT.32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VMSR P0, Rp
VPST
VLDRWT.32 Qd, [Rn]

Argument Preparation

base → Rn 
p → Rp

Result

Qd → result

Supported architectures

MVE

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.8 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRB.8 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRH.16 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

Load consecutive elements from memory into a destination vector register. Each element loaded will be the zero or sign-extended representation of the value in memory. In indexed mode, the target address is calculated from a base register offset by an immediate value. Otherwise, the base register address is used directly. The sum of the base register and the immediate value can optionally be written back to the base register. NOTE: Predicated lanes are zeroed instead of retaining their previous values.

T32 Instruction

VLDRW.32 Qd, [Rn]

Argument Preparation

base → Rn 

Result

Qd → result

Supported architectures

MVE/NEON

Description

"Load a byte, halfword, word, or doubleword from memory at the address contained in either:nna) A base register R[n] plus an offset contained in each element of Q[m], optionally shifted by the element size, ornnb) Each element of Q[m] plus an immediate offset. The base element can optionally be written back, irrespective of predication, with that value incremented by the immediate or by the immediate scaled by the memory element size.nn Each element loaded will be the zero or sign-extended representation of the value in memory. The result is written back into the corresponding element in the destination vector register Q[d]. NOTE: Predicated lanes are zeroed instead of retaining their previous values."

T32 Instruction

VLDRH.U16 Qd, [Rn, Qm]

Argument Preparation

base → Rn 
offset → Qm

Result

Qd → result

Supported architectures

MVE

Description

"Load a byte, halfword, word, or doubleword from memory at the address contained in either:nna) A base register R[n] plus an offset contained in each element of Q[m], optionally shifted by the element size, ornnb) Each element of Q[m] plus an immediate offset. The base element can optionally be written back, irrespective of predication, with that value incremented by the immediate or by the immediate scaled by the memory element size.nn Each element loaded will be the zero or sign-extended representation of the value in memory. The result is written back into the corresponding element in the destination vector register Q[d]. NOTE: Predicated lanes are zeroed instead of retaining their previous values."

T32 Instruction

VLDRH.S32 Qd, [Rn, Qm]

Argument Preparation

base → Rn 
offset → Qm

Result

Qd → result

Supported architectures

MVE

Description

"Load a byte, halfword, word, or doubleword from memory at the address contained in either:nna) A base register R[n] plus an offset contained in each element of Q[m], optionally shifted by the element size, ornnb) Each element of Q[m] plus an immediate offset. The base element can optionally be written back, irrespective of predication, with that value incremented by the immediate or by the immediate scaled by the memory element size.nn Each element loaded will be the zero or sign-extended representation of the value in memory. The result is written back into the corresponding element in the destination vector register Q[d]. NOTE: Predicated lanes are zeroed instead of retaining their previous values."

T32 Instruction

VLDRH.U16 Qd, [Rn, Qm]

Argument Preparation

base → Rn 
offset → Qm

Result

Qd → result

Supported architectures

MVE

Description

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