SIMD ISAs | Neon Intrinsics Reference

Neon Intrinsics

Neon intrinsics are function calls that the compiler replaces with an appropriate Neon instruction or sequence of Neon instructions. Intrinsics provide almost as much control as writing assembly language, but leave the allocation of registers to the compiler, so that developers can focus on the algorithms. It can also perform instruction scheduling to remove pipeline stalls for the specified target processor. This leads to more maintainable source code than using assembly language. Neon Intrinsics is supported by Arm Compilers, gcc and LLVM. The Neon Programmer’s Guide provides more information about intrinsics and Neon programming in general.

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.

int8x8_t vadd_s8 (int8x8_t a, int8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vaddq_s8 (int8x16_t a, int8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vadd_s16 (int16x4_t a, int16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddq_s16 (int16x8_t a, int16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vadd_s32 (int32x2_t a, int32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddq_s32 (int32x4_t a, int32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vadd_s64 (int64x1_t a, int64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddq_s64 (int64x2_t a, int64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vadd_u8 (uint8x8_t a, uint8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vaddq_u8 (uint8x16_t a, uint8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vadd_u16 (uint16x4_t a, uint16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddq_u16 (uint16x8_t a, uint16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vadd_u32 (uint32x2_t a, uint32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddq_u32 (uint32x4_t a, uint32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vadd_u64 (uint64x1_t a, uint64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddq_u64 (uint64x2_t a, uint64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vadd_f32 (float32x2_t a, float32x2_t b)Floating-point add

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

FADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vaddq_f32 (float32x4_t a, float32x4_t b)Floating-point add

Description

A64 Instruction

FADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vadd_f64 (float64x1_t a, float64x1_t b)Floating-point add

Description

A64 Instruction

FADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vaddq_f64 (float64x2_t a, float64x2_t b)Floating-point add

Description

A64 Instruction

FADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

int64_t vaddd_s64 (int64_t a, int64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

A64

uint64_t vaddd_u64 (uint64_t a, uint64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

ADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

A64

int16x8_t vaddl_s8 (int8x8_t a, int8x8_t b)Signed add long

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

SADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddl_s16 (int16x4_t a, int16x4_t b)Signed add long

Description

A64 Instruction

SADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddl_s32 (int32x2_t a, int32x2_t b)Signed add long

Description

A64 Instruction

SADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddl_u8 (uint8x8_t a, uint8x8_t b)Unsigned add long

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

UADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddl_u16 (uint16x4_t a, uint16x4_t b)Unsigned add long

Description

A64 Instruction

UADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddl_u32 (uint32x2_t a, uint32x2_t b)Unsigned add long

Description

A64 Instruction

UADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddl_high_s8 (int8x16_t a, int8x16_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int32x4_t vaddl_high_s16 (int16x8_t a, int16x8_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int64x2_t vaddl_high_s32 (int32x4_t a, int32x4_t b)Signed add long

Description

A64 Instruction

SADDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint16x8_t vaddl_high_u8 (uint8x16_t a, uint8x16_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint32x4_t vaddl_high_u16 (uint16x8_t a, uint16x8_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint64x2_t vaddl_high_u32 (uint32x4_t a, uint32x4_t b)Unsigned add long

Description

A64 Instruction

UADDL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int16x8_t vaddw_s8 (int16x8_t a, int8x8_t b)Signed add wide

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

A64 Instruction

SADDW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 

b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddw_s16 (int32x4_t a, int16x4_t b)Signed add wide

Description

A64 Instruction

SADDW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 

b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddw_s32 (int64x2_t a, int32x2_t b)Signed add wide

Description

A64 Instruction

SADDW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 

b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddw_u8 (uint16x8_t a, uint8x8_t b)Unsigned add wide

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

A64 Instruction

UADDW Vd.8H,Vn.8H,Vm.8B

Argument Preparation

a → Vn.8H 

b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddw_u16 (uint32x4_t a, uint16x4_t b)Unsigned add wide

Description

A64 Instruction

UADDW Vd.4S,Vn.4S,Vm.4H

Argument Preparation

a → Vn.4S 

b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddw_u32 (uint64x2_t a, uint32x2_t b)Unsigned add wide

Description

A64 Instruction

UADDW Vd.2D,Vn.2D,Vm.2S

Argument Preparation

a → Vn.2D 

b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddw_high_s8 (int16x8_t a, int8x16_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 

b → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int32x4_t vaddw_high_s16 (int32x4_t a, int16x8_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 

b → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int64x2_t vaddw_high_s32 (int64x2_t a, int32x4_t b)Signed add wide

Description

A64 Instruction

SADDW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 

b → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint16x8_t vaddw_high_u8 (uint16x8_t a, uint8x16_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.8H,Vn.8H,Vm.16B

Argument Preparation

a → Vn.8H 

b → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint32x4_t vaddw_high_u16 (uint32x4_t a, uint16x8_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.4S,Vn.4S,Vm.8H

Argument Preparation

a → Vn.4S 

b → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

uint64x2_t vaddw_high_u32 (uint64x2_t a, uint32x4_t b)Unsigned add wide

Description

A64 Instruction

UADDW2 Vd.2D,Vn.2D,Vm.4S

Argument Preparation

a → Vn.2D 

b → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int8x8_t vhadd_s8 (int8x8_t a, int8x8_t b)Signed halving add

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vhaddq_s8 (int8x16_t a, int8x16_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vhadd_s16 (int16x4_t a, int16x4_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vhaddq_s16 (int16x8_t a, int16x8_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vhadd_s32 (int32x2_t a, int32x2_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vhaddq_s32 (int32x4_t a, int32x4_t b)Signed halving add

Description

A64 Instruction

SHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vhadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned halving add

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vhaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vhadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vhaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vhadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vhaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned halving add

Description

A64 Instruction

UHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    Elem[result, e, esize] = sum<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vrhadd_s8 (int8x8_t a, int8x8_t b)Signed rounding halving add

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SRHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vrhaddq_s8 (int8x16_t a, int8x16_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vrhadd_s16 (int16x4_t a, int16x4_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vrhaddq_s16 (int16x8_t a, int16x8_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vrhadd_s32 (int32x2_t a, int32x2_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vrhaddq_s32 (int32x4_t a, int32x4_t b)Signed rounding halving add

Description

A64 Instruction

SRHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vrhadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned rounding halving add

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

URHADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vrhaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vrhadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vrhaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vrhadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vrhaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned rounding halving add

Description

A64 Instruction

URHADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    Elem[result, e, esize] = (element1+element2+1)<esize:1>;

V[d] = result;

Supported architectures

v7/A32/A64

int8x8_t vqadd_s8 (int8x8_t a, int8x8_t b)Signed saturating add

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

SQADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vqaddq_s8 (int8x16_t a, int8x16_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vqadd_s16 (int16x4_t a, int16x4_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vqaddq_s16 (int16x8_t a, int16x8_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vqadd_s32 (int32x2_t a, int32x2_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vqaddq_s32 (int32x4_t a, int32x4_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vqadd_s64 (int64x1_t a, int64x1_t b)Signed saturating add

Description

A64 Instruction

SQADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vqaddq_s64 (int64x2_t a, int64x2_t b)Signed saturating add

Description

A64 Instruction

SQADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vqadd_u8 (uint8x8_t a, uint8x8_t b)Unsigned saturating add

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

UQADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vqaddq_u8 (uint8x16_t a, uint8x16_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vqadd_u16 (uint16x4_t a, uint16x4_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vqaddq_u16 (uint16x8_t a, uint16x8_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vqadd_u32 (uint32x2_t a, uint32x2_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vqaddq_u32 (uint32x4_t a, uint32x4_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vqadd_u64 (uint64x1_t a, uint64x1_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vqaddq_u64 (uint64x2_t a, uint64x2_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

v7/A32/A64

int8_t vqaddb_s8 (int8_t a, int8_t b)Signed saturating add

Description

A64 Instruction

SQADD Bd,Bn,Bm

Argument Preparation

a → Bn 

b → Bm

Results

Bd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

int16_t vqaddh_s16 (int16_t a, int16_t b)Signed saturating add

Description

A64 Instruction

SQADD Hd,Hn,Hm

Argument Preparation

a → Hn 

b → Hm

Results

Hd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

int32_t vqadds_s32 (int32_t a, int32_t b)Signed saturating add

Description

A64 Instruction

SQADD Sd,Sn,Sm

Argument Preparation

a → Sn 

b → Sm

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

int64_t vqaddd_s64 (int64_t a, int64_t b)Signed saturating add

Description

A64 Instruction

SQADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

uint8_t vqaddb_u8 (uint8_t a, uint8_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Bd,Bn,Bm

Argument Preparation

a → Bn 

b → Bm

Results

Bd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

uint16_t vqaddh_u16 (uint16_t a, uint16_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Hd,Hn,Hm

Argument Preparation

a → Hn 

b → Hm

Results

Hd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

uint32_t vqadds_u32 (uint32_t a, uint32_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Sd,Sn,Sm

Argument Preparation

a → Sn 

b → Sm

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

uint64_t vqaddd_u64 (uint64_t a, uint64_t b)Unsigned saturating add

Description

A64 Instruction

UQADD Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
integer element1;
integer element2;
integer sum;
boolean sat;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    sum = element1 + element2;
    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
    if sat then FPSR.QC = '1';

V[d] = result;

Supported architectures

A64

int8x8_t vuqadd_s8 (int8x8_t a, uint8x8_t b)Signed saturating accumulate of unsigned value

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

A64 Instruction

SUQADD Vd.8B,Vn.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int8x16_t vuqaddq_s8 (int8x16_t a, uint8x16_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.16B,Vn.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int16x4_t vuqadd_s16 (int16x4_t a, uint16x4_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.4H,Vn.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int16x8_t vuqaddq_s16 (int16x8_t a, uint16x8_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.8H,Vn.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int32x2_t vuqadd_s32 (int32x2_t a, uint32x2_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.2S,Vn.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int32x4_t vuqaddq_s32 (int32x4_t a, uint32x4_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.4S,Vn.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int64x1_t vuqadd_s64 (int64x1_t a, uint64x1_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Dd,Dn

Argument Preparation

a → Dd 

b → Dn

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int64x2_t vuqaddq_s64 (int64x2_t a, uint64x2_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Vd.2D,Vn.2D

Argument Preparation

a → Vd.2D 

b → Vn.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int8_t vuqaddb_s8 (int8_t a, uint8_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Bd,Bn

Argument Preparation

a → Bd 

b → Bn

Results

Bd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int16_t vuqaddh_s16 (int16_t a, uint16_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Hd,Hn

Argument Preparation

a → Hd 

b → Hn

Results

Hd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int32_t vuqadds_s32 (int32_t a, uint32_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Sd,Sn

Argument Preparation

a → Sd 

b → Sn

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int64_t vuqaddd_s64 (int64_t a, uint64_t b)Signed saturating accumulate of unsigned value

Description

A64 Instruction

SUQADD Dd,Dn

Argument Preparation

a → Dd 

b → Dn

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint8x8_t vsqadd_u8 (uint8x8_t a, int8x8_t b)Unsigned saturating accumulate of signed value

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

A64 Instruction

USQADD Vd.8B,Vn.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint8x16_t vsqaddq_u8 (uint8x16_t a, int8x16_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.16B,Vn.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint16x4_t vsqadd_u16 (uint16x4_t a, int16x4_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.4H,Vn.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint16x8_t vsqaddq_u16 (uint16x8_t a, int16x8_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.8H,Vn.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint32x2_t vsqadd_u32 (uint32x2_t a, int32x2_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.2S,Vn.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint32x4_t vsqaddq_u32 (uint32x4_t a, int32x4_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.4S,Vn.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint64x1_t vsqadd_u64 (uint64x1_t a, int64x1_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Dd,Dn

Argument Preparation

a → Dd 

b → Dn

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint64x2_t vsqaddq_u64 (uint64x2_t a, int64x2_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Vd.2D,Vn.2D

Argument Preparation

a → Vd.2D 

b → Vn.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint8_t vsqaddb_u8 (uint8_t a, int8_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Bd,Bn

Argument Preparation

a → Bd 

b → Bn

Results

Bd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint16_t vsqaddh_u16 (uint16_t a, int16_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Hd,Hn

Argument Preparation

a → Hd 

b → Hn

Results

Hd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint32_t vsqadds_u32 (uint32_t a, int32_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Sd,Sn

Argument Preparation

a → Sd 

b → Sn

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

uint64_t vsqaddd_u64 (uint64_t a, int64_t b)Unsigned saturating accumulate of signed value

Description

A64 Instruction

USQADD Dd,Dn

Argument Preparation

a → Dd 

b → Dn

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n];
bits(datasize) result;

bits(datasize) operand2 = V[d];
integer op1;
integer op2;
boolean sat;

for e = 0 to elements-1
    op1 = Int(Elem[operand, e, esize], !unsigned);
    op2 = Int(Elem[operand2, e, esize], unsigned);
    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
    if sat then FPSR.QC = '1';
V[d] = result;

Supported architectures

A64

int8x8_t vaddhn_s16 (int16x8_t a, int16x8_t b)Add returning high narrow

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vaddhn_s32 (int32x4_t a, int32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vaddhn_s64 (int64x2_t a, int64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vaddhn_u16 (uint16x8_t a, uint16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vaddhn_u32 (uint32x4_t a, uint32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vaddhn_u64 (uint64x2_t a, uint64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vaddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 

a → Vn.8H 

b → Vm.8H

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vaddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 

a → Vn.4S 

b → Vm.4S

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vaddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 

a → Vn.2D 

b → Vm.2D

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vaddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 

a → Vn.8H 

b → Vm.8H

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vaddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 

a → Vn.4S 

b → Vm.4S

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vaddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Add returning high narrow

Description

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 

a → Vn.2D 

b → Vm.2D

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vraddhn_s16 (int16x8_t a, int16x8_t b)Rounding add returning high narrow

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int16x4_t vraddhn_s32 (int32x4_t a, int32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int32x2_t vraddhn_s64 (int64x2_t a, int64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint8x8_t vraddhn_u16 (uint16x8_t a, uint16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint16x4_t vraddhn_u32 (uint32x4_t a, uint32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

uint32x2_t vraddhn_u64 (uint64x2_t a, uint64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

v7/A32/A64

int8x16_t vraddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 

a → Vn.8H 

b → Vm.8H

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int16x8_t vraddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 

a → Vn.4S 

b → Vm.4S

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int32x4_t vraddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 

a → Vn.2D 

b → Vm.2D

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint8x16_t vraddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H

Argument Preparation

r → Vd.8B 

a → Vn.8H 

b → Vm.8H

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint16x8_t vraddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S

Argument Preparation

r → Vd.4H 

a → Vn.4S 

b → Vm.4S

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

uint32x4_t vraddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)Rounding add returning high narrow

Description

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D

Argument Preparation

r → Vd.2S 

a → Vn.2D 

b → Vm.2D

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(2*datasize) operand1 = V[n];
bits(2*datasize) operand2 = V[m];
bits(datasize) result;
integer round_const = if round then 1 << (esize - 1) else 0;
bits(2*esize) element1;
bits(2*esize) element2;
bits(2*esize) sum;

for e = 0 to elements-1
    element1 = Elem[operand1, e, 2*esize];
    element2 = Elem[operand2, e, 2*esize];
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    sum = sum + round_const;
    Elem[result, e, esize] = sum<2*esize-1:esize>;

Vpart[d, part] = result;

Supported architectures

A64

int8x8_t vmul_s8 (int8x8_t a, int8x8_t b)Multiply

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmulq_s8 (int8x16_t a, int8x16_t b)Multiply

Description

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmul_s16 (int16x4_t a, int16x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmulq_s16 (int16x8_t a, int16x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmul_s32 (int32x2_t a, int32x2_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmulq_s32 (int32x4_t a, int32x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmul_u8 (uint8x8_t a, uint8x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmulq_u8 (uint8x16_t a, uint8x16_t b)Multiply

Description

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmul_u16 (uint16x4_t a, uint16x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 

b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmulq_u16 (uint16x8_t a, uint16x8_t b)Multiply

Description

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 

b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmul_u32 (uint32x2_t a, uint32x2_t b)Multiply

Description

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmulq_u32 (uint32x4_t a, uint32x4_t b)Multiply

Description

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmul_f32 (float32x2_t a, float32x2_t b)Floating-point multiply

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vmulq_f32 (float32x4_t a, float32x4_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

v7/A32/A64

poly8x8_t vmul_p8 (poly8x8_t a, poly8x8_t b)Polynomial multiply

Description

Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

PMUL Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 

b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

poly8x16_t vmulq_p8 (poly8x16_t a, poly8x16_t b)Polynomial multiply

Description

A64 Instruction

PMUL Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 

b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vmul_f64 (float64x1_t a, float64x1_t b)Floating-point multiply

Description

A64 Instruction

FMUL Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vmulq_f64 (float64x2_t a, float64x2_t b)Floating-point multiply

Description

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x2_t vmulx_f32 (float32x2_t a, float32x2_t b)Floating-point multiply extended (by element)

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_f32 (float32x4_t a, float32x4_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x1_t vmulx_f64 (float64x1_t a, float64x1_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_f64 (float64x2_t a, float64x2_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32_t vmulxs_f32 (float32_t a, float32_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Sm

Argument Preparation

a → Sn 

b → Sm

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64_t vmulxd_f64 (float64_t a, float64_t b)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x2_t vmulx_lane_f32 (float32x2_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 

v → Vm.2S 

0 << lane << 1

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_lane_f32 (float32x4_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 

v → Vm.2S 

0 << lane << 1

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x1_t vmulx_lane_f64 (float64x1_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 

v → Vm.1D 

0 << lane << 0

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_lane_f64 (float64x2_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 

v → Vm.1D 

0 << lane << 0

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32_t vmulxs_lane_f32 (float32_t a, float32x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 

v → Vm.2S 

0 << lane << 1

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64_t vmulxd_lane_f64 (float64_t a, float64x1_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 

v → Vm.1D 

0 << lane << 0

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x2_t vmulx_laneq_f32 (float32x2_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]

Argument Preparation

a → Vn.2S 

v → Vm.4S 

0 << lane << 3

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x4_t vmulxq_laneq_f32 (float32x4_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]

Argument Preparation

a → Vn.4S 

v → Vm.4S 

0 << lane << 3

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x1_t vmulx_laneq_f64 (float64x1_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 

v → Vm.2D 

0 << lane << 1

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vmulxq_laneq_f64 (float64x2_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]

Argument Preparation

a → Vn.2D 

v → Vm.2D 

0 << lane << 1

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32_t vmulxs_laneq_f32 (float32_t a, float32x4_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]

Argument Preparation

a → Sn 

v → Vm.4S 

0 << lane << 3

Results

Sd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64_t vmulxd_laneq_f64 (float64_t a, float64x2_t v, const int lane)Floating-point multiply extended (by element)

Description

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]

Argument Preparation

a → Dn 

v → Vm.2D 

0 << lane << 1

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(idxdsize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2 = Elem[operand2, index, esize];

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    if mulx_op then
        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
    else
        Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x2_t vdiv_f32 (float32x2_t a, float32x2_t b)Floating-point divide

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

FDIV Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 

b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float32x4_t vdivq_f32 (float32x4_t a, float32x4_t b)Floating-point divide

Description

A64 Instruction

FDIV Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 

b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x1_t vdiv_f64 (float64x1_t a, float64x1_t b)Floating-point divide

Description

A64 Instruction

FDIV Dd,Dn,Dm

Argument Preparation

a → Dn 

b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

float64x2_t vdivq_f64 (float64x2_t a, float64x2_t b)Floating-point divide

Description

A64 Instruction

FDIV Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 

b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);

V[d] = result;

Supported architectures

A64

int8x8_t vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Multiply-add to accumulator

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B 

c → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B 

c → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H 

c → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H 

c → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S 

c → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S 

c → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B 

c → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B 

c → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H 

c → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H 

c → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S 

c → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Multiply-add to accumulator

Description

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S 

c → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmla_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

v7/A32/A64

float32x4_t vmlaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

v7/A32/A64

float64x1_t vmla_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

A64

float64x2_t vmlaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Floating-point multiply-add to accumulator

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

A64

int16x8_t vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)Signed multiply-add long

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SMLAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 

b → Vn.8B 

c → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 

b → Vn.4H 

c → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 

b → Vn.2S 

c → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)Unsigned multiply-add long

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

UMLAL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 

b → Vn.8B 

c → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 

b → Vn.4H 

c → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2D 

b → Vn.2S 

c → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 

b → Vn.16B 

c → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

int32x4_t vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 

b → Vn.8H 

c → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

int64x2_t vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)Signed multiply-add long

Description

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 

b → Vn.4S 

c → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

uint16x8_t vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vd.8H 

b → Vn.16B 

c → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

uint32x4_t vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vd.4S 

b → Vn.8H 

c → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

uint64x2_t vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)Unsigned multiply-add long

Description

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.4S

Argument Preparation

a → Vd.2D 

b → Vn.4S 

c → Vm.4S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

A64

int8x8_t vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)Multiply-subtract from accumulator

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B 

c → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B 

c → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H 

c → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H 

c → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S 

c → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S 

c → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8B 

b → Vn.8B 

c → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vd.16B 

b → Vn.16B 

c → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4H 

b → Vn.4H 

c → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vd.8H 

b → Vn.8H 

c → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vd.2S 

b → Vn.2S 

c → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vd.4S 

b → Vn.4S 

c → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) operand3 = V[d];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    product = (UInt(element1)*UInt(element2))<esize-1:0>;
    if sub_op then
        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
    else
        Elem[result, e, esize] = Elem[operand3, e, esize] + product;

V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vmls_f32 (float32x2_t a, float32x2_t b, float32x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

v7/A32/A64

float32x4_t vmlsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

v7/A32/A64

float64x1_t vmls_f64 (float64x1_t a, float64x1_t b, float64x1_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

A64

float64x2_t vmlsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)Multiply-subtract from accumulator

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1

Argument Preparation

a → N/A 

b → N/A 

c → N/A

Results

N/A → result

Supported architectures

A64

int16x8_t vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)Signed multiply-subtract long

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

A64 Instruction

SMLSL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vd.8H 

b → Vn.8B 

c → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;
    Elem[result, e, 2*esize] = accum;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)Signed multiply-subtract long

Description

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vd.4S 

b → Vn.4H 

c → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) operand3 = V[d];
bits(2*datasize) result;
integer element1;
integer element2;
bits(2*esize) product;
bits(2*esize) accum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    product = (element1*element2)<2*esize-1:0>;
    if sub_op then
        accum = Elem[operand3, e, 2*esize] - product;
    else
        accum = Elem[operand3, e, 2*esize] + product;