SIMD ISAs | Neon Intrinsics Reference

Neon Intrinsics

Neon intrinsics are function calls that the compiler replaces with an appropriate Neon instruction or sequence of Neon instructions. Intrinsics provide almost as much control as writing assembly language, but leave the allocation of registers to the compiler, so that developers can focus on the algorithms. It can also perform instruction scheduling to remove pipeline stalls for the specified target processor. This leads to more maintainable source code than using assembly language. Neon Intrinsics is supported by Arm Compilers, gcc and LLVM. The Neon Programmer's Guide for Armv8-A provides more information about intrinsics and Neon programming in general.

Here are two introduction guides on using Neon Intrinsics with Android:

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter text in the search box, then click the button.

For more information about the concepts and usage related to the Neon intrinsics, see the Arm C Language Extensions documentation.

int8x8_t vadd_s8 (int8x8_t a, int8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int8x16_t vaddq_s8 (int8x16_t a, int8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int16x4_t vadd_s16 (int16x4_t a, int16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddq_s16 (int16x8_t a, int16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int32x2_t vadd_s32 (int32x2_t a, int32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddq_s32 (int32x4_t a, int32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int64x1_t vadd_s64 (int64x1_t a, int64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddq_s64 (int64x2_t a, int64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x8_t vadd_u8 (uint8x8_t a, uint8x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.8B,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Results

Vd.8B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint8x16_t vaddq_u8 (uint8x16_t a, uint8x16_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.16B,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Results

Vd.16B → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x4_t vadd_u16 (uint16x4_t a, uint16x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.4H,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Results

Vd.4H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddq_u16 (uint16x8_t a, uint16x8_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.8H,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x2_t vadd_u32 (uint32x2_t a, uint32x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddq_u32 (uint32x4_t a, uint32x4_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x1_t vadd_u64 (uint64x1_t a, uint64x1_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddq_u64 (uint64x2_t a, uint64x2_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

v7/A32/A64

float32x2_t vadd_f32 (float32x2_t a, float32x2_t b)Floating-point add

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

A64 Instruction

            FADD Vd.2S,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Results

Vd.2S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR[]);

V[d] = result;

Supported architectures

v7/A32/A64

float32x4_t vaddq_f32 (float32x4_t a, float32x4_t b)Floating-point add

Description

A64 Instruction

            FADD Vd.4S,Vn.4S,Vm.4S

Argument Preparation

a → Vn.4S 
b → Vm.4S

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR[]);

V[d] = result;

Supported architectures

v7/A32/A64

float64x1_t vadd_f64 (float64x1_t a, float64x1_t b)Floating-point add

Description

A64 Instruction

            FADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR[]);

V[d] = result;

Supported architectures

A64

float64x2_t vaddq_f64 (float64x2_t a, float64x2_t b)Floating-point add

Description

A64 Instruction

            FADD Vd.2D,Vn.2D,Vm.2D

Argument Preparation

a → Vn.2D 
b → Vm.2D

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(2*datasize) concat = operand2:operand1;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    if pair then
        element1 = Elem[concat, 2*e, esize];
        element2 = Elem[concat, (2*e)+1, esize];
    else
        element1 = Elem[operand1, e, esize];
        element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPAdd(element1, element2, FPCR[]);

V[d] = result;

Supported architectures

A64

int64_t vaddd_s64 (int64_t a, int64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

A64

uint64_t vaddd_u64 (uint64_t a, uint64_t b)Add

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

A64 Instruction

            ADD Dd,Dn,Dm

Argument Preparation

a → Dn 
b → Dm

Results

Dd → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n];
bits(datasize) operand2 = V[m];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if sub_op then
        Elem[result, e, esize] = element1 - element2;
    else
        Elem[result, e, esize] = element1 + element2;

V[d] = result;

Supported architectures

A64

int16x8_t vaddl_s8 (int8x8_t a, int8x8_t b)Signed add long

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

A64 Instruction

            SADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int32x4_t vaddl_s16 (int16x4_t a, int16x4_t b)Signed add long

Description

A64 Instruction

            SADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int64x2_t vaddl_s32 (int32x2_t a, int32x2_t b)Signed add long

Description

A64 Instruction

            SADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint16x8_t vaddl_u8 (uint8x8_t a, uint8x8_t b)Unsigned add long

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

A64 Instruction

            UADDL Vd.8H,Vn.8B,Vm.8B

Argument Preparation

a → Vn.8B 
b → Vm.8B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint32x4_t vaddl_u16 (uint16x4_t a, uint16x4_t b)Unsigned add long

Description

A64 Instruction

            UADDL Vd.4S,Vn.4H,Vm.4H

Argument Preparation

a → Vn.4H 
b → Vm.4H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

uint64x2_t vaddl_u32 (uint32x2_t a, uint32x2_t b)Unsigned add long

Description

A64 Instruction

            UADDL Vd.2D,Vn.2S,Vm.2S

Argument Preparation

a → Vn.2S 
b → Vm.2S

Results

Vd.2D → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

v7/A32/A64

int16x8_t vaddl_high_s8 (int8x16_t a, int8x16_t b)Signed add long

Description

A64 Instruction

            SADDL2 Vd.8H,Vn.16B,Vm.16B

Argument Preparation

a → Vn.16B 
b → Vm.16B

Results

Vd.8H → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

int32x4_t vaddl_high_s16 (int16x8_t a, int16x8_t b)Signed add long

Description

A64 Instruction

            SADDL2 Vd.4S,Vn.8H,Vm.8H

Argument Preparation

a → Vn.8H 
b → Vm.8H

Results

Vd.4S → result

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = Vpart[n, part];
bits(datasize) operand2 = Vpart[m, part];
bits(2*datasize) result;
integer element1;
integer element2;
integer sum;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    if sub_op then
        sum = element1 - element2;
    else
        sum = element1 + element2;
    Elem[result, e, 2*esize] = sum<2*esize-1:0>;

V[d] = result;

Supported architectures

A64

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