In order to use the intrinsics the Advanced SIMD architecture must be supported, and some specific instructions may or may not be enabled in any case. When the following macros are defined and equal to 1, the corresponding features are available:
- Advanced SIMD is supported by the compiler
- Always 1 for AArch64
- Neon floating-point operations are supported
- Always 1 for AArch64
- Crypto instructions are available.
- Cryptographic Neon intrinsics are therefore available.
- The fused multiply-accumulate instructions are available.
- Neon intrinsics which use these are therefore available.
This list is not exhaustive and further macros are detailed in the Arm C Language Extensions document.
There are three major categories of data type available in
arm_neon.h which follow these patterns:
- Scalar data types
- Vector data types
- Vector array data types
baserefers to the fundamental data type.
Wis the width of the fundamental type.
Lis the number of scalar data type instances in a vector data type, for example an array of scalars.
Nis the number of vector data type instances in a vector array type, for example a struct of arrays of scalars.
L are such that the vector data types are 64 or 128 bits long, and so fit completely into a Neon register.
N corresponds with those instructions which operate on multiple registers at once.
In our earlier code we encountered an example of all three:
As per the Arm C Language Extensions, the function prototypes from
arm_neon.h follow a common pattern. At the most general level this is:
ret v[p][q][r]name[u][n][q][x][_high][_lane | laneq][_n][_result]_type(args)
Be wary that some of the letters and names are overloaded, but in the order above:
- the return type of the function.
- short for
vectorand is present on all the intrinsics.
- indicates a pairwise operation. (
valuemay be present).
- indicates a saturating operation (with the exception of
vqtb[l][x]in AArch64 operations where the
qindicates 128-bit index and result operands).
- indicates a rounding operation.
- the descriptive name of the basic operation. Often this is an Advanced SIMD instruction, but it does not have to be.
- indicates signed-to-unsigned saturation.
- indicates a narrowing operation.
- postfixing the name indicates an operation on 128-bit vectors.
- indicates an Advanced SIMD scalar operation in AArch64. It can be one of
d(that is, 8, 16, 32, or 64 bits).
- In AArch64, used for widening and narrowing operations involving 128-bit operands. For widening 128-bit operands,
highrefers to the top 64-bits of the source operand(s). For narrowing, it refers to the top 64-bits of the destination operand.
- indicates a scalar operand supplied as an argument.
- indicates a scalar operand taken from the lane of a vector.
_laneqindicates a scalar operand taken from the lane of an input vector of 128-bit width. (
left | rightmeans only
- the primary operand type in short form.
- the function's arguments.