Overview Why you should care about the ISA Instruction sets in the Arm architecture Instruction set resources Simple sequential execution Registers in AArch64 - general-purpose registers Registers in AArch64 - other registers Registers in AArch64 - system registers Data processing - arithmetic and logic operations Data processing - floating point Data processing - bit manipulation Data processing - extension and saturation Data processing - format conversion Data processing - vector data Loads and stores Loads and stores - size Loads and stores - zero and sign extension Loads and stores - addressing Loads and stores - load pair and store pair Loads and stores - using floating point registers Program flow Program flow - loops and decisions Program flow - generating condition code Program flow - conditional select instructions Function calls Procedure Call Standard System calls Check your knowledge Related information Next steps
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According to the PCS, for the function uint32_t foo(uint64_t a, uint64_t b), which registers will used to pass in a and b, and to return the result?
a will be passed in
X0and b will be passed inX1. The result will be returned inW0. -
What instruction does a 64-bit floating-point addition of D0 and D1, then places the result in D5?
FADD D5, D0, D1 -
What does this instruction do? LDRSH W0, [X1, #8]
It loads 16-bits from the address
X1+8and sign extends the result to 32 bits, placing the result inW0. -
What instruction is most commonly used for a function return?
RET -
Which register is used to store the return address when calling a function?
X30, which can also be referred asLR. -
What does executing an SVC instruction in an application do?
It would cause an exception, leading to entry into the OS.
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After executing SUB W5, W8, W4, what is in the upper 32 bits of X5?
0s (zeroes). Whenever aWregister is written, the upper 32 bits of the mappedXregister are zeroed.