Overview Why you should care about the ISA Instruction sets in the Arm architecture Instruction set resources Simple sequential execution Registers in AArch64 - general-purpose registers Registers in AArch64 - other registers Registers in AArch64 - system registers Data processing - arithmetic and logic operations Data processing - floating point Data processing - bit manipulation Data processing - extension and saturation Data processing - format conversion Data processing - vector data Loads and stores Loads and stores - size Loads and stores - zero and sign extension Loads and stores - addressing Loads and stores - load pair and store pair Loads and stores - using floating point registers Program flow Program flow - loops and decisions Program flow - generating condition code Program flow - conditional select instructions Function calls Procedure Call Standard System calls Check your knowledge Related information Next steps
Single Page Download PDF

Arithmetic and logic operations

The basic format of logical and integer arithmetic instructions is:

The parts of the instruction are as follows:

  • Operation. This defines what the instruction does. For example, ADD does addition and AND performs a logical AND.
    An S can be added to the operation to set flags. For example, ADD becomes ADDS. This s tells the processor to update the ALU flags based on the result of instruction. We discuss ALU flags in the section on generating condition code.
  • Destination: The destination of the instruction is always a register, and specifies where the result of the operation is placed. Most instructions have a single destination register. A few instructions have two destination registers. When the destination is a W register, the upper 32 bits of the corresponding X register are set to 0.
  • Operand 1: This will always be a register. This is the first input to the instruction.
  • Operand 2: This will be a register or a constant, and is the second input to the instruction.
    When operand 2 is a register, it may include an optional shift.
    When operand 2 is a constant, it is encoded within the instruction itself. This means that the range of constants available is limited.

You should be aware of a couple of special cases, such as the MOV and MVN instructions. MOV moves a constant, or the contents of another register, into the register specified as the destination. MOV and MVN only require a single input operand, which can be either a register or a constant, as shown here:

 MOV	X0, #1

sets: X0 = 1

 MVN	W0, W1

sets: W0 = ~W1

Previous Next