Overview Why you should care about the ISA Instruction sets in the Arm architecture Instruction set resources Simple sequential execution Registers in AArch64 - general-purpose registers Registers in AArch64 - other registers Registers in AArch64 - system registers Data processing - arithmetic and logic operations Data processing - floating point Data processing - bit manipulation Data processing - extension and saturation Data processing - format conversion Data processing - vector data Loads and stores Loads and stores - size Loads and stores - zero and sign extension Loads and stores - addressing Loads and stores - load pair and store pair Loads and stores - using floating point registers Program flow Program flow - loops and decisions Program flow - generating condition code Program flow - conditional select instructions Function calls Procedure Call Standard System calls Check your knowledge Related information Next steps
Zero and sign extension
By default, when a sub-register-sized quantity of data is loaded, the rest of the register is zeroed, as shown in this figure:

Note: Remember that whenever a W
register is written, the top half of the X
register is zeroed.
Adding an S to the operation causes the value to be sign extended instead. How far the size extension goes depends on whether the target is a W
or X
register, as shown in this figure:

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Task: If the byte at address 0x8000 contains the value 0x1F, what would be the result of LDRSB X4, be?
LDRSB
is performing a byte load with sign extension to 64 bits. The most significant bit of the loaded value will be replicated to fill the 64-bit register. The loaded value,0x1F
, has its top bit clear. Therefore, the value inX4
will be0x0000_0000_0000_001F
.