Describing memory in AArch64
The mapping between virtual and physical address spaces is defined in a set of translation tables, also sometimes called page tables. For each block or page of virtual addresses, the translation tables provide the corresponding physical address and the attributes for accessing that page.
Each translation table entry is called a block or page descriptor. In most cases, the attributes come from this descriptor.
This diagram shows an example block descriptor, and the attribute fields within it:
Important attributes are:
- SH - The shareable attribute
- AP - The access permission
- UXN and PXN – Execution permissions
Remember these attributes, because we will revisit them later in this guide.
Some memory attributes can be specified in the Table descriptors in higher-level tables. These are hierarchical attributes. This applies to Access Permission, Execution Permissions, and the Physical Address space.
If these bits are set then they override the lower level entries, and if the bits are clear the lower level entries are used unmodified. An example, using PXNTable (execution permission) is shown here:
From Armv8.1-A, you can disable support for setting the access permission and execution permissions using the hierarchical attributes in a table descriptor. This is controlled via the relevant TCR_ELx register. When disabled, the bits previously used for the hierarchical controls are available to software to use for other things.
To summarize, the attributes for an address come from the translation tables. Translation tables are situated in memory and are used to store the mappings between virtual and physical addresses. The tables also contain the attributes for physical memory locations.
The translation tables are accessed by the Memory Management Unit (MMU).
What happens if the MMU is disabled? This is an important question to address when writing code that will run immediately after reset.
When the Stage 1 MMU is disabled:
- All data accesses are Device_nGnRnE. We will explain this later in this guide.
- All instruction fetches are treated as cacheable.
- All addresses have read/write access and are executable.
For Exception levels covered by virtualization, when Stage 2 is disabled the attributes from Stage 1 are used unmodified.