The external debug model is used when the debugger is hosted outside of the Processing Element (PE) that is being debugged. Debug state is the basis of the external debug model. The external debugger programs the debug logic to cause debug state when debug events occur. When the PE enters debug state:
- The PE stops executing instructions from the location that is indicated by the Program Counter. Instead, the PE is controlled through the external debug interface that is also called the ED interface (External Debug interface).
- Through the external debug interface, the Instruction Transfer Register (ITR) is used to pass instructions to the PE to execute in debug state.
- Through the external debug interface, the Debug Communications Channel (DCC) passes data between the PE and the debugger.
- The PE cannot service interrupts in debug state.
External debug is also called halting-debug mode. The following diagram illustrates the debug setup of an Arm core that is using an ED interface:
External debug is useful for:
- Hardware bring-up. Hardware bring-up is debugging during the stage of development when a system is first powered up and the software functionality is not fully available.
- Debugging PEs that are deeply embedded inside systems
In external debug mode, debug registers are accessed using external debug interface. The means that access to external debug interface is IMPLEMENTATION DEFINED. However, most Armv8-A systems implement a Debug Access Port (DAP), so that off-chip external debuggers can access external debug interface. On-chip external debuggers, for example, debuggers that are using a second PE to debug a PE, use a memory mapped interface to access an external debug interface.
External debug and halt-mode debug registers are usually prefixed with ED, for example,
EDSCR. Some of the important ED registers are:
- EDSCR: External Debug Status and Control Register
- EDECR: External Debug Execution Control Register
Now let’s look at how to enable external debug, which is also called Halting debug. There are no global enable bits for Halting debug. There are separate enable bits for each Halting debug event.
Breakpoints and watchpoints are resources that are shared between self-hosted and external debuggers. Setting EDSCR.HDE to one causes breakpoints or watchpoints to halt the PE.
External debuggers sometimes need to authenticate themselves. Without this authentication, some Arm implementations can prohibit halting. Details of the authentication are IMPLEMENTATION DEFINED. Authentication can be hierarchical. For example, some levels of authentication might enable halting during Non-secure execution of the PE. A next level of authentication might be needed to allow halting during Secure execution of the PE.