Introduction to debug

Debug provides the ability to observe and control the CPU and system environment while executing software on a deeply embedded processor. The ability to debug helps to fix bugs in the software and to optimize the software for performance. The debug logic that is an integrated part of the Arm cores helps to achieve these goals.

What is debug logic?

The debug logic of the processor is responsible for generating debug events. Debug logic includes comparators and other hardware logic that enable debug events like breakpoints, single stepping, and watchpoints. 

The following diagram shows debug logic in an Arm core:


Debug logic is fully integrated with an Arm core and is not an entity outside the core.

Depending on the configuration of the debug logic, debug events like breakpoint and watchpoint cause either debug exception or debug state. Let’s look at debug exceptions and debug state in more detail.

What is a debug exception?

Debug events cause a debug exception if debug logic is configured for self-hosted debug. Debug exception is a synchronous exception that is programmed by the debugger, which is part of the high-level software or operating system. The debugger is also called a self-hosted debugger.

Debug exceptions are the basis of the self-hosted debug model.

What is debug state?

If debug logic is configured for external debug, debug events halt the Processing Element (PE), and the PE enters debug state. While in debug state, the PE stops executing the instructions that are pointed by the Program Counter. The PE is controlled by the external debug interface.  

Debug state is the basis of the external debug model.

Debug logic can be configured for a debug event to cause debug exceptions or entry to debug state. A single instance of debug event is never converted into both a debug exception and an entry to debug state.

The following diagram illustrates the sequence of actions after a debug event corresponding to the configuration of debug logic:


The configuration of debug logic and the type of debug event determine whether debug events are converted into exceptions, entry to debug state, or are ignored.

How to access debug logic

The Armv8-A debug architecture defines multiple mechanisms to access debug logic as registers. Some debug components must be made accessible through particular interfaces. However, it is an IMPLEMENTATION DEFINED choice to enable access to debug logic through one of the following:

  • External debug interface
  • System register interface
  • Memory mapped interface

The following diagram describes access to Debug register for each type of interface:

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