Sending and receiving Software Generated Interrupts

Software Generated Interrupts (SGIs) are interrupts that software can trigger by writing to a register in the interrupt controller.

Generating SGIs

An SGI is generated by writing to one of the following SGI registers in the CPU interface:

System register interface Description
ICC_SGI0R_EL1 Generates a Secure Group 0 interrupt.
ICC_SGI1R_EL1 Generates a Group 1 interrupt, for the current Security state of the PE.
ICC_ASGI1R_EL1 Generates a Group 1 interrupt, for the other Security state of the PE.

You can see the basic format of the SGI registers in the following diagram:

Controlling the SGI ID

The SGI ID field controls which INTID is generated. As described in Interrupt types, INTIDs 0-15 are used for SGIs.

Controlling the target

The IRM (Interrupt Routing Mode) field in the SGI registers controls which PE or PEs an SGI is sent to. There are two options:

  • IRM = 0
    The interrupt is sent to <aff3>.<aff2>.<aff1>.<Target List>, where <target list> is encoded as 1 bit for each affinity 0 node under <aff1>. This means that the interrupt can be sent to a maximum of 16 PEs, which might include the originating PE.
  • IRM = 1
    The interrupt is sent to all connected PEs, except the originating PE (self).

Controlling the Security state and grouping

The Security state and grouping of SGIs is controlled by:

  • The SGI register, ICC_SGI0R_EL1, ICC_SGI1R_EL1, or ICC_ASGIR_EL1, that is written by software on the originating PE.
  • The GICR_IGROUPR0 and GICR_IGRPMODR0 registers of the target PE or PEs.

Software executing in Secure state can send both Secure and Non-secure SGIs. Whether software executing in Non-secure state can generate Secure SGIs is controlled by GICR_NSACR. This register can only be accessed by software executing in Secure state. The following table shows the GIC determines whether an interrupt is forwarded or not by inspecting:

  • The Security state of the originating PE.
  • The interrupt handling configuration of the PE which the interrupt is targeting.
  • The SGI register.
Security state of sending PE SGI register written Configuration on receiving PE Forwarded?
Secure EL3/EL1 ICC_SGI0R_EL1 Secure Group 0 Yes
Secure Group 1 No
Non-secure Group 1 No
ICC_SGI1R_EL1 Secure Group 0 No (*)
Secure Group 1 Yes
Non-Secure Group 1 No
ICC_ASGI1R_EL1 Secure Group 0 No
Secure Group 1 No
Non-secure Group 1 Yes
Non-secure EL2/EL1 ICC_SGI0R_EL1 Secure Group 0 Configurable by GICR_NSACR (*)
Secure Group 1 No
Non-secure Group 1 No
ICC_SGI1R_EL1 Secure Group 0 Configurable by GICR_NSACR (*)
Secure Group 1 Configurable by GICR_NSACR
Non-secure Group 1 Yes
ICC_ASGI1R_EL1 Secure Group 0 Configurable by GICR_NSACR (*)
Secure Group 1 Configurable by GICR_NSACR
Non-secure Group 1 No

* This table assumes that GICD_CTLR.DS==0. When GICD_CTLR.DS==1, the SGIs marked with (*) are also forwarded.

Comparison of GICv3 and GICv2

In Arm CoreLink GICv2, SGI INTIDs are banked by the originating PE and the target PE. This means that a given PE could have the same SGI INTID pending a maximum of eight times, once from each PE in the system.

In Arm CoreLink GICv3, SGIs are only banked by the target PE. This means that a given PE can only have one instance of an SGI INTID pending.

Let’s illustrate this difference with an example. PEs A and B simultaneously send SGI INTID 5 to PE C, as shown here:

How many interrupts will C receive?

  • For GICv2: Two interrupts
    The GIC will receive both the interrupts from A and B. The order of the two interrupts depends on the individual design and the precise timing. The two interrupts can be distinguished by the fact that the ID of the originating PE is prefixed to the INTID that is returned by GICC_IAR.
  • For GICv3: One interrupt
    Because the originating PE does not bank the SGI, the same interrupt cannot be pending on two PEs. Therefore, C only receive one interrupt, with ID 5, no prefix.

The example assumes that the two interrupts are sent simultaneously or almost simultaneously. If C were able to acknowledge the first SGI before the second SGI arrived, then C would see two interrupts in GICv3.

Note: During legacy operation, that is when GICD_CTLR.ARE=0, the behavior of SGIs is the same as in Arm CoreLink GICv2.

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