What is a Generic Interrupt Controller?

A Generic Interrupt Controller (GIC) takes interrupts from peripherals, prioritizes them, and delivers them to the appropriate processor core. The following diagram shows a GIC taking interrupts from n different peripherals, and distributing them to two different processors.

A brief history of the Arm CoreLink GIC

Like the Arm architecture, the GIC architecture has evolved over time. The following table summarizes the major releases of the GIC specification and the processors that they are typically used with.

GIC versions Key features Typically used with
GICv1 Support for up to eight PEs
Support for up to 1020 interrupt IDs
Support for two Security states
Arm Cortex-A5 MPCore
Arm Cortex-A9 MPCore
Arm Cortex-R4
Arm Cortex-R5 MPCore
Arm Cortex-R7 MPCore
Arm Cortex-R8 MPCore
GICv2 All key features of GICv1
Support for virtualization
Arm Cortex-A7 MPCore
Arm Cortex-A15 MPCore
Arm Cortex-A17 MPCore
GICv3 All key features of GICv2
Support for more than eight PEs
Support for message-signaled interrupts
Support for more than 1020 interrupt IDs
System register access to the CPU Interface registers
An enhanced security model that separates Secure and Non-secure Group 1 interrupts
Arm Cortex-A3x MPCore
Arm Cortex-A5x MPCore
Arm Cortex-A7x MPCore
GICv4 All key features of GICv3
Direct injection of virtual interrupts Arm Cortex-A3x MPCore
Arm Cortex-A5x MPCore
Arm Cortex-A7x MPCore

This guide covers Arm CoreLink GICv3 and GICv4, which are used by most Armv8-A and Armv8-R designs.

Arm CoreLink GICv3 and GICv4 have also received minor updates since they were released:

  • GICv3.1 added support additional wired interrupts, Secure virtualization and Memory System Resource
  • Partitioning and Monitoring (MPAM)
  • GICv4.1 extended virtualization support to cover direct-injection of virtual Software Generated Interrupts (SGIs)

Note: GICv2m is an extension to GICv2 to add support for message-signaled interrupts. For more information contact Arm Support.

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