Atomic accesses

An atomic access is a term for a series of accesses to a memory region. Atomic accesses are used by masters when they would like to perform a sequence of accesses to a particular memory region, while being sure that the original data in the region are not corrupted by writes from other masters. This sequence is commonly a read, modify, and write sequence.

There are two types of atomic accesses:

  • Locked

    While a master is performing a transaction sequence with locked accesses, accesses from any other masters to the same slave are rejected.

  • Exclusive

    When a master successfully performs a transaction sequence with exclusive accesses, other masters can access the slave but not the memory region that is being accessed.

Locked accesses

Locked transactions should only be used for legacy devices. AXI4 does not support locked transactions, but AXI3 implementations must support locked transactions.

Before a master can start a locked sequence of transactions, it must ensure that it has no other transactions waiting to complete.

A transaction with the AxLOCK signal set indicates a locked transaction. A locked sequence of transactions forces the interconnect to reject access to the slave from any other masters.

The locked sequence must always complete with a final transaction that does not have the AxLOCK signal set. This final transaction is still included in the locked sequence, but effectively removes the lock to allow other masters access to the slave.

Because locked accesses require the interconnect to prevent any other transactions occurring while the locked sequence is in progress, they have an important impact on the interconnect performance.

The following diagram shows the AXI locked access operation with an example using two masters, M0 and M1:

 

Before a master can start a locked sequence of transactions, the master must ensure that it has no other transactions that are waiting to complete.

When M0 uses a lock signal for a transaction to indicate that it is a locked transaction, then the interconnect uses an arbiter to ensure that only M0 can access the targeted slave. The interconnect blocks any accesses from M1 until an unlocked transaction from M0 completes.

The following diagram shows how locked access works with a sequence of transactions:

 

The steps in this example are as follows:

  1. Master M0 initiates a sequence of READ, MODIFY, and WRITE.

    The first transaction, READ, has the LOCK signal asserted, indicating that it starts a locked transaction.

  2. The interconnect locks out any other transactions.

    From this point, master M1 has no access to the slave.

  3. The final transaction in the sequence, WRITE, does not have the LOCK signal asserted. This transaction indicates the end of the locked sequence.

    The interconnect removes the lock, and other masters can now access the slave.

 

Exclusive accesses

With AXI 4, exclusive accesses perform atomic operations more efficiently than locked accesses. This is because exclusive accesses use the interconnect bandwidth more effectively.

In an exclusive access sequence, other masters can access the slave at the same time, but only one master will be granted access to the same memory range.

The mechanism that is used for exclusive accesses can provide semaphore-type operations without requiring the bus to remain dedicated to a particular master during the operation. This means that the bus access latency and the maximum achievable bandwidth are not affected.

Exclusive accesses can be composed of more than one data transfer, but all the transactions must have identical address channel attributes.

A hardware exclusive access monitor is required by the slave to record the transaction information for the exclusive sequence so that it knows the memory range that is being accessed and the identity of the master performing the access.

If no other master accesses the monitored range until the exclusive sequence is completed, the access is atomic.

The slave is open to accesses from other masters, resulting in overall increased fairness in bandwidth utilization for the system.

Exclusive access hardware monitor operation

The basic mechanism of an exclusive access is governed by an exclusive access monitor that you must implement.

The following diagram shows an example where the master M0 performs an exclusive read from an address:

The response from the exclusive access monitor hardware is one of the following:

  • EXOKAY

    The value is read, and the ID of the transaction is stored in the exclusive access monitor hardware.

  • OKAY

    The value is read, but there is no support for exclusive access, and the master should treat this response as an error for the exclusive operation.

At some later time, if EXOKAY was received during the exclusive read, M0 attempts to complete the exclusive sequence by performing an exclusive write to the same address. The exclusive write uses the same transaction ID as the exclusive read.

The response from the exclusive access monitor hardware is one of the following:

  • EXOKAY

    No other master has written to that location since the exclusive read access, so the write is successful. In this case, the exclusive write updates memory.

  • OKAY

    Another master, for example M1, has written to the location since the exclusive read access, so the write fails. In this case, the memory location is not updated.

Some slaves require extra logic to support exclusive access. The exclusive access monitoring hardware monitors only one address for each transaction ID. It should be implemented so that it can monitor every possible exclusive ID that can be seen.

Exclusive transaction pairs: both pass

This section describes an example of two successful exclusive access sequences that both pass.

The following diagram shows a system containing a master, with its AXI master interface, and a slave:

 

The slave interface includes exclusive access monitoring hardware that can save the ID and the address accessed for each transaction.

The following table describes the different transactions in the example sequence. All transactions in the table are exclusive accesses:

Transaction number Read or write Transaction ID Address Data xRESP
1 R 0 0xA000 0x1 EXOKAY
2 R 1 0xB000 0x2 EXOKAY
3 W 0 0xA000 0x3 EXOKAY
4 W 1 0xB000 0x4 EXOKAY

The transaction sequence shown in the previous table proceeds as follows:

  1. The first transaction is the master, which performs a read exclusive transaction with ID 0 from address 0xA000.

    The exclusive access monitoring hardware saves the ID and address of this transaction in its table, and the slave responds with the read data, 0x1.

    Because exclusive accesses are correctly supported for this slave, the exclusive access monitoring hardware responds with an EXOKAY response.

  2. Next, the master performs a new read exclusive transaction with ID 1 from address 0xB000.

    Again, the exclusive access monitoring hardware saves the details of this new transaction in the table, and the slave responds with the read data, 0x2.

    Because exclusive accesses are correctly supported for this slave, the exclusive access monitoring hardware again responds with an EXOKAY response.

    At this moment in our example there are two separate exclusive sequences ongoing.

  3. After the master has completed its operation, it performs a write exclusive transaction with ID 0 to address 0xA000.

    The exclusive access monitoring hardware checks the detail of this transaction in the table and, because of the existing record with ID 0 and address 0xA000, responds to the master with an EXOKAY response. This means that no other master has accessed this memory location, and the slave updates it with the new value it receives, which in this example is 0x3.

    The exclusive access monitoring hardware removes the ID and address for this transaction from its table, because the exclusive access sequence for that address location is now complete.

  4. Finally, the master performs a new write exclusive transaction with ID 1 to address 0xB000.

    The exclusive access monitoring hardware checks the detail of this transaction in its table. Seeing an existing record with ID 1 and address 0xB000, it again responds to the master with an EXOKAY response. This means that no other master has accessed this memory location, and the slave updates it with the new value received, which in our example is 0x4.

    Again, the exclusive access monitoring hardware removes the ID and address for this transaction from its table, because the exclusive access sequence for that address location is now complete.

Exclusive transaction pairs: one pass, one fail

This section describes an example of two exclusive access sequences, where the first one succeeds and the second one fails.

The following diagram shows a system containing a master, with its AXI master interface, and a slave:

 

The slave interface includes exclusive access monitoring hardware that can save the ID and the address accessed for each transaction.

The following table describes the different transactions in the example sequence. All transactions in the table are exclusive accesses:

Transaction number Read or write Transaction ID Address Data xRESP
1 R 0 0xA000 0x1 EXOKAY
2 R 1 0xA000 0x1 EXOKAY
3 W 0 0xA000 0x3 EXOKAY
4 W 1 0xA000 0x4 OKAY

The transaction sequence shown in the previous table proceeds as follows:

  1. The first transaction is the master performing a read exclusive transaction with ID 0 from address 0xA000.

    The exclusive access monitoring hardware saves the ID and address of this transaction in its table, and the slave responds with the read data, 0x1.

    Because exclusive accesses are correctly supported for this slave, the exclusive access monitoring hardware responds with an EXOKAY response.

  2. Later, the master performs a new read exclusive transaction with ID 1 from the same address as the first transaction, 0xA000.

    The exclusive access monitoring hardware saves the detail of this new transaction in the table, and the slave responds with the read data, 0x1.

    Again, because exclusive accesses are correctly supported for this slave, the exclusive access monitoring hardware responds with an EXOKAY response.

    At this moment in our example, we have two different ongoing exclusive sequences to the same memory location.

  3. After the master has completed its operation, it performs an exclusive write transaction with ID 0 to address 0xA000.

    The exclusive access monitoring hardware checks the detail of this transaction in its table and, seeing a record with ID 0 and address 0xA000, responds to the master with an EXOKAY response. This means that no other master has updated this memory location, and the slave can update it with the new value received, which in our example is 0x3.

    Because the content of the address location 0xA000 has been modified, the exclusive access monitoring hardware removes from its table all the entries that match that location address.

  4. Finally, the master performs a new write exclusive transaction with ID 1 again to address 0xA000.

    The exclusive access monitoring hardware checks the detail of this transaction in its table. Not finding any records with the address 0xA000, it responds with an OKAY response.

    The OKAY response means that a previous write operation has been performed on this memory location which updated the data. In this case, the slave cannot update the memory location with the new value, 0x4.

    This situation is an exclusive access failure. In this case, the master must restart the full exclusive access sequence beginning with the exclusive read and then the exclusive write again.

This example demonstrates how exclusive accesses implement non-blocking behavior. It is this behavior that provides greater system throughput when compared with LOCK accesses.

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