AXI protocol overview
AXI is an interface specification that defines the interface of IP blocks, rather than the interconnect itself.
The following diagram shows how AXI is used to interface an interconnect component:
In AX3 and AXI4, there are only two AXI interface types, master and slave. These interface types are symmetrical. All AXI connections are between master interfaces and slave interfaces.
AXI interconnect interfaces contain the same signals, which makes integration of different IP relatively simple. The previous diagram shows how AXI connections join master and slave interfaces. The direct connection gives maximum bandwidth between the master and slave components with no extra logic. And with AXI, there is only a single protocol to validate.
AXI in a multi-master system
The following diagram shows a simplified example of an SoC system, which is composed of masters, slaves, and the interconnect that links them all:
An Arm processor is an example of a master, and a simple example of a slave is a memory controller.
The AXI protocol defines the signals and timing of the point-to-point connections between masters and slaves.
Note: The AXI protocol is a point-to-point specification, not a bus specification. Therefore, it describes only the signals and timing between interfaces.
The previous diagram shows that each AXI master interface is connected to a single AXI slave interface. Where multiple masters and slaves are involved, an interconnect fabric is required. This interconnect fabric also implements slave and master interfaces, where the AXI protocol is implemented.
The following diagram shows that the interconnect is a complex element that requires its own AXI master and slave interfaces to communicate with external function blocks:
The following diagram shows an example of an SoC with various processors and function blocks:
The previous diagram shows all the connections where AXI is used. You can see that AXI3 and AXI4 are used within the same SoC, which is common practice. In such cases, the interconnect performs the protocol conversion between the different AXI interfaces.
The AXI specification describes a point-to-point protocol between two interfaces: a master and a slave. The following diagram shows the five main channels that each AXI interface uses for communication:
Write operations use the following channels:
- The master sends an address on the Write Address (AW) channel and transfers data on the Write Data (W) channel to the slave.
- The slave writes the received data to the specified address. Once the slave has completed the write operation, it responds with a message to the master on the Write Response (B) channel.
Read operations use the following channels:
- The master sends the address it wants to read on the Read Address (AR) channel.
The slave sends the data from the requested address to the master on the Read Data (R) channel.
The slave can also return an error message on the Read Data (R) channel. An error occurs if, for example, the address is not valid, or the data is corrupted, or the access does not have the right security permission.
Note: Each channel is unidirectional, so a separate Write Response channel is needed to pass responses back to the master. However, there is no need for a Read Response channel, because a read response is passed as part of the Read Data channel.
Using separate address and data channels for read and write transfers helps to maximize the bandwidth of the interface. There is no timing relationship between the groups of read and write channels. This means that a read sequence can happen at the same time as a write sequence.
Each of these five channels contains several signals, and all these signals in each channel have the prefix as follows:
- AW for signals on the Write Address channel
- AR for signals on the Read Address channel
- W for signals on the Write Data channel
- R for signals on the Read Data channel
- B for signals on the Write Response channel
Note: B stands for buffered, because the response from the slave happens after all writes have completed.
Main AXI features
The AXI protocol has several key features that are designed to improve bandwidth and latency of data transfers and transactions, as you can see here:
- Independent read and write channels
- AXI supports two different sets of channels, one for write operations, and one for read operations. Having two independent sets of channel helps to improve the bandwidth performances of the interfaces. This is because read and write operations can happen at the same time.
- Multiple outstanding addresses
- AXI allows for multiple outstanding addresses. This means that a master can issue transactions without waiting for earlier transactions to complete. This can improve system performance because it enables parallel processing of transactions.
- No strict timing relationship between address and data operations
- With AXI, there is no strict timing relationship between the address and data operations. This means that, for example, a master could issue a write address on the Write Address channel, but there is no time requirement for when the master has to provide the corresponding data to write on the Write Data channel.
- Support for unaligned data transfers
- For any burst that is made up of data transfers wider than one byte, the first bytes accessed can be unaligned with the natural address boundary. For example, a 32-bit data packet that starts at a byte address of
0x1002is not aligned to the natural 32-bit address boundary.
- Out-of-order transaction completion
- Out-of-order transaction completion is possible with AXI. The AXI protocol includes transaction identifiers, and there is no restriction on the completion of transactions with different ID values. This means that a single physical port can support out-of-order transactions by acting as several logical ports, each of which handles its transactions in order.
- Burst transactions based on start address
- AXI masters only issue the starting address for the first transfer. For any following transfers, the slave will calculate the next transfer address based on the burst type.