Channel signals

This section introduces the main AXI signals and attributes, and explains how they are used to improve system performance.

The AXI protocol defines five channels: three for write signals, and two for read signals.

Write channel signals

The channels used for a write transaction are:

  • Write Address
  • Write Data
  • Write Response

The following table shows the Write Address channel signals:

Write Address (AW) channel signals AXI version
AWVALID AXI3 and AXI4
AWREADY AXI3 and AXI4
AWADDR[31:0 AXI3 and AXI4
AWSIZE[2:0] AXI3 and AXI4
AWBURST[1:0] AXI3 and AXI4
AWCACHE[3:0] AXI3 and AXI4
AWPROT[2:0 AXI3 and AXI4
AWID[x:0] AXI3 and AXI4
AWLEN[3:0]
AWLEN[7:0]
AXI3 only
AXI4 only
AWLOCK[1:0]
AWLOCK
AXI3 only
AXI4 only
AWQOS[3:0] AXI4 only
AWREGION[3:0] AXI4 only
AWUSER[x:0] AXI4 only

The following table shows the Write Data channel signals:

Write Data (W) channel signals AXI version
WVALID AXI3 and AXI4
WREADY AXI3 and AXI4
WLAST AXI3 and AXI4
WDATA[x:0] AXI3 and AXI4
WSTRB[x:0] AXI3 and AXI4
WID[x:0] AXI3 only
WUSER[x:0 AXI4 only

The following table shows the Write Response channel signals:

Write Response (B) channel signals AXI version
BVALID AXI3 and AXI4
BREADY AXI3 and AXI4
BRESP[1:0 AXI3 and AXI4
BID[x:0] AXI3 and AXI4
BUSER[x:0 AXI4 only

All the signals in each channel have the same prefix:

  • AW for the Write Address channel
  • W for the Write Data channel
  • B for the Write Response channel

There are some differences between the AXI3 protocol and the AXI4 protocol for the write channels:

  • For the write address channel, the AWLEN signal is wider for the AXI4 protocol. Therefore, AXI4 is able to generate longer bursts than AXI3.
  • AXI4 reduces the AWLOCK signal to a single bit to only accommodate exclusive transfers because locked transfers are not supported.
  • AXI4 adds the AWQOS signal to the AW channel. This signal supports the concept of quality of service (QoS) in the AXI4 protocol.
  • AXI4 adds the AWREGION signal to the AW channel. This signal supports slave regions which allow for multiple logical interfaces from a single physical slave interface.
  • AXI4 removes the WID signal from the W channel. This is because write data reordering is no longer allowed.
  • AXI4 adds user-defined signals to each channel.

Read channel signals

The channels used for a read transaction are:

  • Read Address
  • Read Data

The following table shows the Read Address channel signals:

Read Address (AR) channel signals AXI version
ARVALID AXI3 and AXI4
AREADY AXI3 and AXI4
ARADDR[31:0 AXI3 and AXI4
ARSIZE[2:0 AXI3 and AXI4
ARBURST[1:0 AXI3 and AXI4
ARCACHE[3:0 AXI3 and AXI4
ARPROT[2:0 AXI3 and AXI4
ARID[x:0 AXI3 and AXI4
ARLEN[3:0]
ARLEN[7:0]
AXI3 only
AXI4 only
ARLOCK[1:0]
ARLOCK
AXI3 only
AXI4 only
ARQOS[3:0 AXI4 only
ARREGION[3:0 AXI4 only
ARUSER[x:0 AXI4 only
The following table shows the Read Data channel signals:
Read Data (R) channel signals AXI version
RVALID AXI3 and AXI4
READY AXI3 and AXI4
RLAST AXI3 and AXI4
RDATA[x:0] AXI3 and AXI4
RRESP[1:0] AXI3 and AXI4
RID[x:0] AXI3 and AXI4
RUSER[x:0] AXI4 only

All the signals in each channel have the same prefix:

  • AR for the Read Address channel
  • R for the Read Data channel

There are some differences between the AXI3 protocol and the AXI4 protocol for the read channels:

  • For the AXI4 protocol, the read address length signal ARLEN is wider. Therefore, AXI4 is able to generate longer read bursts than AXI3.
  • AXI4 reduces the ARLOCK signal to a single bit to only accommodate exclusive transfers because locked transfers are not supported.
  • As with the write channel signals, the concepts of quality of service and slave regions apply to read transactions. These use the ARQOS and ARREGION signals in the AR channel.
  • AXI4 adds user-defined signals to the two read channels.

Data size, length, and burst type

Each read and write transaction has attributes that specify the data length, size, and the burst signal attributes for that transaction.

In the following list of attributes, x stands for write and read, so they apply to both the Write Address channel and the Read Address channel:

  • AxLEN describes the length of the transaction in the number of transfers.
    • For AXI3, AxLEN[3:0] has 4 bits, which specifies a range of 1-16 transfers in a transaction.
    • For AXI4, AxLEN[7:0] has 8 bits, which specifies a range of 1-256 data transfers in a transaction.
  • AxSize[2:0] describes the maximum number of bytes to transfer in each data transfer. Three bits of encoding indicate 1, 2, 4, 8, 16, 32, 64, or 128 bytes per transfer.
  • AxBURST[1:0] describes the burst type of the transaction: fixed, incrementing, or wrapping.

    The following table shows the different properties of these burst types:

    Value Burst type Usage notes Length (number of transfers) Alignment
    0x00 FIXED Reads the same address repeatedly. Useful for FIFOs. 1-16 Fixed byte lanes only defined by start address and size.
    0x01 INCR

    Incrementing burst.

    The slave increments the address for each transfer in the burst from the address for the previous transfer.

    The incremental value depends on the size of the transfer, as defined by the AxSIZE attribute.

    Useful for block transfers.

    AXI3: 1-16
    AXI4: 1-256
    Unaligned transfers are supported.
    0x10 WRAP

    Wrapping burst.

    Similar to an incrementing burst, except that if an upper address limit is reached, the address wraps around to a lower address.

    Commonly used for cache line accesses.

    2, 4, 8, or 16 The start address must be aligned to the transfer size.
    0x11 RESERVED Not for use. - -

Protection level support

AXI provides access permissions signals, AWPROT and ARPROT, that can protect against illegal transactions downstream in the system. For example, if a transaction does not have the correct level of protection, a memory controller could refuse read or write access by using these signals.

This is useful for security solutions like Arm TrustZone, where a processor has two separate states, Secure and Non-secure.

AxPROT defines three levels of access protection, as shown in the following diagram:

The AxPROT bit allocations specify the following attributes:

  • AxPROT[0] (P) identifies an access as unprivileged or privileged:

    • 1 indicates privileged access.
    • 0 indicates unprivileged access.

    Although some processors support multiple levels of privilege, the only distinction that AXI can provide is between privileged and unprivileged access.

  • AxPROT[1] (NS) identifies an access as Secure or Non-secure:

    • 1 indicates a Non-secure transaction.
    • 0 indicates a Secure transaction.
  • AxPROT[2] (I) indicates whether the transaction is an instruction access or a data access:

    • 1 indicates an instruction access.
    • 0 indicates a data access.

    The AXI protocol defines this indication as a hint.

    It is not accurate in all cases, for example, where a transaction contains a mix of instruction and data items.

    The Arm AXI specification for both AXI 3 and AXI 4 recommends that a master sets bit 2 to zero to indicate a data access, unless the access is specifically known to be an instruction access.

Cache support

Modern SoC systems often contain caches that are placed in several points of the system. For example, the level 2 cache might be external to the processor, or the level 3 caches might be in front of the memory controller.

To support systems that use different caching policies, the AWCACHE and ARCACHE signals indicate how transactions are required to progress through a system.

The following diagram shows the AxCACHE bit allocations:

The AxCACHE bit allocations specify the following attributes:

  • AxCACHE [0] (B) is the bufferable bit.

    When this bit is set to 1, the interconnect or any component can delay the transaction reaching its final destination for any number of cycles.

    The bufferable bit indicates whether the response can come from an intermediate point, or whether the response must come from the destination slave.

  • AxCACHE [1] is the cacheable bit in AXI3, or the modifiable bit in AXI4.

    This bit indicates that the attributes of a transaction at the final destination do not have to match the attributes of the original transaction.

    For writes, setting the modifiable bit means that several different writes can be merged, or a single write can be broken into multiple transactions.

    For reads, setting the modifiable bit means that the contents of a location can be prefetched, or the values from a single fetch can be used for multiple read transactions.

  • AxCACHE [2] is the RA bit.

    The RA bit indicates that on a read, the allocation of the transaction is recommended, but not mandatory.

    If either AxCACHE [2] or AxCACHE [3] is asserted, then the transaction must be looked up in a cache as it could have been allocated in this cache by another master.

  • AxCACHE [3] is the WA bit.

    The WA bit indicates that on a write, the allocation of the transaction is recommended, but not mandatory.

    If either AxCACHE [2] or AxCACHE [3] is asserted, then the transaction must be looked up in a cache as it could have been allocated in this cache by another master.

Note: If AxCACHE [1], the cacheable bit, is not asserted, then AxCACHE [2] and AxCACHE [3] cannot be asserted.

The reason for including read and write allocation on both read and write address buses is that it allows a system-level cache to optimize its performance.

For example, consider a cache that sees a read access defined as "write-allocate, but not read-allocate". In this case, the cache knows that the address might be stored in the cache because it could have been allocated on a previous write, and therefore it must do a cache lookup.

However, now consider that the cache sees a read access that is defined as "no write-allocate and no read-allocate". In this case, the cache knows that the address has not been allocated in the cache. The cache can avoid the lookup and immediately pass the transaction through to the other side. The cache can only do this if it knows both the read and write allocate for every transaction.

It is not a requirement that caches operate in this way, but the AXI protocol is defined with RA and WA for both reads and writes to allow this mode of operation if you or your cache designer want to implement it.

Response signaling

AXI provides response signaling for both read and write transactions.

For read transactions, the response information from the slave is signaled on the read data channel using RRESP.

For write transactions, the response information is signaled on the write response channel using BRESP.

RRESP and BRESP are both composed of two bits, and the encoding of these signals can transfer four responses, as shown in the following table:

Response code Description
00 - OKAY

Normal access success or exclusive access failure.

OKAY is the response that is used for most transactions. OKAY indicates that a normal access has been successful.

This response can also indicate that an exclusive access has failed. An exclusive access is when more than one master can access a slave at once, but these masters cannot access the same memory range.

01 - EXOKAY

Exclusive access okay.

EXOKAY indicates that either the read or write portion of an exclusive access has been successful.

10 – SLVERR

Slave error.

SLVERR is used when the access has reached the slave successfully, but the slave wants to return an error condition to the originating master.

This indicates an unsuccessful transaction. For example, when there is an unsupported transfer size attempted, or a write access attempted to read-only location.

11 - DECERR

Decode error.

DECERR is often generated by an interconnect component to indicate that there is no slave at the transaction address.

Write data strobes

The write data strobe signal is used by a master to tell a slave which bytes of the data bus are required. Write data strobes are useful for cache accesses for efficient movement of sparse data arrays. In addition to using write data strobes, you can optimize data transfers using unaligned start addresses.

The write channel has one strobe bit per byte on the data bus. These bits make the WSTRB signal.

A master must ensure that the write strobes are set to 1 only for byte lanes that contain valid data.

For example, consider a 64-bit write data bus. The WSTRB signal has 8 bits, one for each byte. The following diagram shows how example WSTRB values specify which byte lanes are valid:

Looking at the first example, we suppose that the valid data are only in the top six significant bytes of the data bus, from byte 7 to byte 2. This means that the master has to control the WSTRB signal with the hexadecimal value 0xFC.

Similarly, the remaining examples specify valid data bus byte lanes as follows:

  • Valid data only in bytes 2, 3, 4, and 5 of the data bus requires a WSTRB signal value of 0x3C.
  • Valid data only in bytes 0 and 7 of the data bus requires a WSTRB signal value of 0x81.
  • Valid data only in bytes 3, 5, 6, and 7 of the data bus requires a WSTRB signal value of 0xE8.

Byte lane strobes offer efficient movement of sparse data arrays. Using this method, write transactions can be early terminated by setting the remaining transfer byte lane strobes to 0, although the remaining transfers must still be completed. The WSTRB signal can also change between transfers in a transaction.

There is no equivalent signal for the read channel. This is because the master indicates the transfer required and can mask out any unwanted bytes received from the slave.

Atomic accesses with the lock signal

The AxLOCK signal is used to indicate when atomic accesses are being performed. See Atomic accesses for more information and an explanation of the concept and operation of exclusive access transfers.

The AXI protocol provides two mechanisms to support atomicity:

  • Locked accesses

    A locked transfer locks the channel, which remains locked until an unlocked transfer is generated. Locked accesses are similar to the mechanism supported with the AHB protocol.

    When a master uses the AxLOCK signals for a transaction to show that it is a locked transaction, then the interconnect must ensure that only that master can access the targeted slave region, until an unlocked transaction from the same master completes. An arbiter within the interconnect must enforce this restriction. Because locked accesses require the interconnect to prevent any other transactions occurring while the locked sequence is in progress, they can have an important impact on the interconnect performance.

    Locked transactions should only be used for legacy devices. Only AXI3 supports locked accesses. AXI4 does not support locked accesses.

  • Exclusive accesses

    Exclusive accesses are more efficient than locked transactions, and they allow multiple masters to access a slave at the same time.

    The exclusive access mechanism enables the implementation of semaphore-type operations, without requiring the bus to remain locked to a particular master during the operation.

Because locked accesses are not as efficient as exclusive accesses, and most components do not require locked transactions, they have been removed from the AXI4 protocol.

In AXI3, the AxLOCK signal consists of two bits with the following values:

  • 0b00 - Normal
  • 0b01 - Exclusive
  • 0b10 - Locked
  • 0b11 - Reserved

In AXI4, the AxLOCK signal consists of one bit, with the following values:

  • 0b0 - Normal
  • 0b1 - Exclusive

Quality of service

The AXI4 protocol introduces extra signals to support the quality of service (QoS).

Quality of service allows you to prioritize transactions allowing you to improve system performance, by ensuring that more important transactions are dealt with higher priority.

There are two quality of service signals:

  • AWQOS is sent on the Write Address channel for each write transaction.
  • ARQOS is sent on the Read Address channel for each read transaction.

Both signals are 4 bits wide, where the value 0x0 indicates the lowest priority, and the value 0xF indicates the highest priority.

The default system-level implementation of quality of service is that any component with a choice of more than one transaction processes the transaction with the higher QoS value first.

The following diagram shows an example system with a Direct Memory Controller (DMC), specifically the DMC-400. This controller manages transactions to DRAM:

In practice, some elements, like the CPU, require memory accesses that are far more important than those of other components, like the GPU or the VPU.

When appropriate QoS values are assigned to transactions, the interconnect can arbitrate higher priority transaction ahead of lower priority transactions and the DMC reorders transactions to ensure that the correct priority is given.

Region signaling

Region signaling is a new optional feature in AXI4.

When you use region identifiers, it means that a single physical interface on a slave can provide multiple logical interfaces. Each logical interface can have a different location in the system address map.

When the region identifier is used, the slave does not have to support the address decode between the different logical interfaces.

Region signaling uses two 4-bit region identifiers, AWREGION and ARREGION. These region identifiers can uniquely identify up to 16 different regions.

User signals

The AXI4 interface signal set has the option to include a set of user-defined signals, called the User signals.

User signals can be used on each channel to transfer extra custom control information between master and slave components. These signals are optional and do not have to be supported on all channels. If they are used, then the width of the User signals is defined by the implementation and can be different on each channel.

Note: Because the AXI protocol does not define the functions of these User signals, interoperability issues can arise if two components use the same User signals in a way that is incompatible.

AXI channel dependencies

The AXI protocol defines dependencies between the different channels.

Three of the main dependencies are as follows:

  • WLAST transfer must complete before BVALID is asserted.

    • The master must send all the write data before a write response can be seen by the master.

      This dependency does not exist in AXI3 but is introduced for AXI4:

      • In AXI3, the address does not have to be seen before a write response is sent.
      • In AXI4, all of the data and the address must have been transferred before the master can see a write response.
  • RVALID cannot be asserted until ARADDR has been transferred.

    • The slave cannot transfer any read data without it seeing the address first. This is because the slave cannot send data back to the master if it does not know the address that the data will be read from.
  • WVALID can assert before AWVALID.

    • A master could use the Write Data channel to send data to the slave, before communicating the address where the slave should write these data.
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