Translation granule

A translation granule is the smallest block of memory that can be described. Nothing smaller can be described, only larger blocks, which are multiples of the granule.

Armv8-A supports three different granule sizes: 4KB, 16KB, and 64KB.

The granule sizes that a processor supports are IMPLEMENTATION DEFINED and are reported by ID_AA64MMFR0_EL1. All Arm Cortex-A processors support 4KB and 64KB. The selected granule is the smallest block that can be described in the latest level table. Larger blocks can also be described. This table shows the different block sizes for each level of table based on the selected granule:

Level of table

4KB granule

16KB granule

64KB granule 

Size per entry

Bits used to index 

Size per entry 

Bits used to index 

Size per entry 

Bits used to index 

























* There are restrictions on using 52-bit addresses. When the selected granule is 4KB or 16KB, the maximum virtual address region size is 48 bits. Similarly, output physical addresses are limited to 48 bits. It is only when the 64KB granule is used that the full 52 bits can be used.

Note: TCR_EL1 has two separate fields that control the granule size for the kernel space and the user space virtual address ranges. These fields are called TG1 for kernel space and TG0 for user space. A potential problem for programmers is that these two fields have different encodings.

The starting level of address translation

Together, the granule and the size of the virtual address space control the starting level of address translation.

The previous table summarized the block size (size of virtual address range covered by a single entry) for each granule at each level of table. From the block size, you can work out which bits of the virtual address are used to index each level of table.

Let us take the 4KB granule as an example. This diagram shows the bits that are used to index the different levels of table for a 4KB granule:

A diagram showing starting level of translation.

Imagine that, for a configuration, you set the size of the virtual address space, TCR_ELx.T0SZ, to 32. Then the size of the virtual address space, in address bits, is calculated as:

64 - T0SZ = 32-bit address space (address bits 31:0)

If we look at the previous 4KB granule diagram again, level 0 is indexed by bits 47:39. With a 32-bit address space you do not have these bits. Therefore, the starting level of translation for your configuration is level 1.

Next, imagine you set T0SZ to 34:

64 - T0SZ = 30-bit address space (address bits 29:0)

This time, you do not have any other bits that are used to index the level 0 table or the level 1 table, so the starting level of translation for your configuration is level 2.

As the previous diagram shows, when the size of the virtual address space reduces, you need fewer levels of tables to describe it.

These examples are based on using the 4KB granule. The same principle applies when using 16KB and 64KB granules, but the address bits change.

Registers that control address translation

Address translation is controlled by a combination of system registers:

    M - Enable Memory Management Unit (MMU).
    C - Enable for data and unified caches.
    EE - Endianness of translation table walks.
  • TTBR0_ELx and TTBR1_ELx
    BADDR - Physical address (PA) (or intermediate physical address, IPA, for EL0/EL1) of start of translation table.
    ASID - The Address Space Identifier for Non-Global translations.
  • TCR_ELx
    PS/IPS - Size of PA or IPA space, the maximum output address size.
    TnSZ - Size of address space covered by table.
    TGn - Granule size.
    SH/IRGN/ORGN - Cacheability and shareability to be used by MMU table walks.
    TBIn - Disabling of table walks to a specific table.
  • MAIR_ELx
    Attr - Controls the Type and cacheability in Stage 1 tables.

MMU disabled

When the MMU is disabled for a stage of translation, all addresses are flat-mapped. Flat mapping means that the input and output addresses are the same.

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