Alignment and endianness
An access is described as aligned if the address is a multiple of the element size.
STR instructions this means the size of the access. For example, a
LDRH instruction loads a 16-bit value and must be from an address which is a multiple of 16 bits to be considered aligned.
STP instructions load and store a pair of elements, respectively. To be aligned, the address must be a multiple of the size of the elements, not the combined size of both elements. For example:
LDP X0, X1, [X2]
This loads two 64-bit values, 128 bits in total. The address in X2 needs to be a multiple of 64 bits to be considered aligned.
The same principle applies to vector loads and stores.
When the address is not a multiple of the element size, the access is unaligned. Unaligned accesses are allowed to addresses marked as Normal, but not to Device regions. An unaligned access to a Device region will trigger an exception (alignment fault).
Unaligned accesses to regions marked as Normal can be trapped by setting
SCTLR_ELx.A. If this bit is set, unaligned accesses to Normal regions also generate alignment faults.
In Armv8-A, instruction fetches are always treated as Little Endian.
For data accesses, it is IMPLEMENTATION DEFINED whether both Little and Big Endian are supported. And if only one is supported, it is IMPLEMENTATION DEFINED which one is supported.
For processors that support both Big and Little endian, it is configured per Exception level.
Note: If you cannot remember the definition of IMPLEMENTATION DEFINED, read about it in Introducing the Arm Architecture.
Arm’s Cortex-A processors support both Big and Little endian.