This guide introduces the basic principles of memory access ordering. Memory ordering, and the use of barriers, is a big topic. For an introduction start here:
Memory ordering guide (coming soon).
We skipped over describing the cacheability and shareability attributes. These are discussed here:
Caches for temporalness guide (coming soon).
Armv8.5-A introduced support for Branch Target Instructions (BTI). BTI support is controlled by the GP bit in the Stage 1 translation tables. Branch Target Instructions are discussed in:
Security - ROP and JOP guide (coming soon).
If are you are interested in the full details of translation process, it is described fully in pseudo code. The translation pseudo code is included with the XML for the instruction set. A good place to start is the
Describing memory in Armv8-A
Cacheability of instruction fetches are a bit more complicated than you might think. This topic is covered in Caches and Coherency guide (coming soon).
Note: For EL0 and EL1, this behaviour can be partly overridden using the virtualization controls. This topic is covered in Virtualization.
Cacheability and Shareability attributes
Caches and coherency guide (coming soon).
Combining Stage 1 and Stage 2 attributes
Translation, both Stage 1 and 2, are discussed in more detail in Memory Management.
For background information see Virtualization.