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What are the Security states and physical address spaces in the Arm architecture?
The Security states in the Arm architecture are Secure state and Non-secure state. The physical address spaces in the Arm architecture are the Secure physical address space and the Non-secure physical address space.
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For each Exception level, what determines whether the processor is in Secure state or Non-secure state?
For EL0/1/2, the
SCR_EL3.NSbit. EL3 is always in Secure state. -
While in Non-secure state, can software access the Secure physical address space?
No. While in Non-secure state, virtual addresses always map to Non-secure physical addresses.
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Can an access to SP:0x80000 hit on a cache line containing NP:0x80000?
No.
SP:0x80000areNP:0x80000are different locations, so there is no cache hit. -
What do Trusted Base System Architecture (TBSA) and Trusted Board Boot Requirements (TBBR) provide guidance on?
TBBR gives guidance on booting, and TBSA gives guidance on system architecture.
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What is the purpose of a TrustZone Address Space Controller (TZASC)?
A TZASC allows a memory to be partitioned into Secure and Non-secure regions.