The Arm AMBA (Advanced Microcontroller Bus Architecture) protocols are an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.
- AMBA Adaptive Traffic Profile (ATP) specification defines a simple and concise abstraction to express the performance and traffic characteristics of system device interfaces.
- AMBA 5 Coherent Hub Interface (CHI) specification adds a new protocol for the interface architecture, highly scalable SoCs required by many server and networking applications.
- AMBA 5 Advanced High-performance Bus 5 (AHB5) is the latest addition to the AMBA family, complementing the Armv8-M architecture to extend the TrustZone security foundation from the processor to the system.
- AMBA AXI and ACE Protocol Specification (AXI3, AXI4, AXI5, ACE and ACE5) - Download the latest specification document.
- AMBA 5 DTI Specification - Download the latest specification document.
- AMBA Generic Flash Bus GFB outlines a new way of designing Non-Volatile Memory.
- AMBA 4 ACE - AXI Coherency Extensions - Used in big.LITTLE systems for smartphones, tablets, etc.
- AMBA 4 AXI4 - AXI4 is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters.
- AMBA 4 LPI – Low Power Interfaces – Used for power and clock management of SoC components.
- AMBA 3 AXI - Advanced eXtensible Interface - The most widespread AMBA interface. Connectivity up to 100's of Masters and Slaves in complex SoCs.
- AMBA3 AHB-Lite specification - Advanced High-Performance Bus - The main system bus in microcontroller usage.
- AMBA 3 APB - Advanced Peripheral Bus - Minimal gate count for peripherals.
- AMBA 3 ATB - Advanced Trace Bus - For moving trace data around the chip, see CoreSight Debug and Trace.