AMBA 4 Overview

The AMBA 4 specifications introduce more interface protocols on top of the AMBA 3 specifications. These include ACE, the AXI Coherency Extensions, as well as other protocols. It is targeted at high bandwidth, high-clock-frequency system designs and includes features that make it suitable for high-speed interconnect, typical in mobile and consumer applications.


The AMBA 4 AXI and ACE specification defines a series of protocols, specifically the AXI4, AXI4-Lite, ACE, and ACE-Lite.


The ACE protocol, AXI Coherency Extensions add three additional channels for sharing data between ACE master caches and hardware control of cache maintenance. ACE also adds barrier support to enforce ordering of multiple outstanding transactions, thus minimizing CPU stalls waiting for preceding transactions to complete. Distributed Virtual Memory (DVM) signaling maintains virtual memory mapping across multiple masters.


The ACE-Lite protocol is a small subset of ACE signals that offer I/O, or one-way coherency, where ACE masters maintain the cache coherency of ACE-Lite masters. ACE-Lite masters can still snoop ACE master caches, but other masters cannot snoop ACE-Lite master's caches. ACE-Lite also supports barriers.


The AXI4 protocol is an update to AXI3 that enhances the performance and use of the interconnect, when used by multiple masters. It includes the following enhancements:

  • Support for burst lengths up to 256 beats
  • Quality of Service signaling
  • Support for multiple region interfaces

  • AXI4-Lite

    The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interface are:

  • All transactions are burst length of one
  • All data accesses are the same size as the width of the data bus
  • Exclusive accesses are not supported
  • AMBA AXI and ACE Specifications


    The AMBA 4 AXI-Stream specification defines the AXI4-Stream protocol, which is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:

  • Supports single and multiple data streams using the same set of shared wires
  • Support for multiple data widths within the same interconnect
  • Ideal for implementation in FPGA
  • AMBA AXI-Stream Specification


    The Q-Channel and P-Channel LPI protocol is designed to manage clock and power features of SoC components. Key features of the LPI protocol are:

  • Q-Channel to manage autonomous hierarchical clock gating and simple component power control.
  • P-Channel to manage more complex power control features to increase power efficiency.
  • AMBA LPI Specification