AMBA 5 Overview

AMBA 5 is the latest generation of freely-available AMBA protocol specifications. It introduces the Coherent Hub Interface (CHI) architecture, which defines the interfaces for the connection of fully coherent processors and high-performance interconnects. AMBA 5 also introduces the AXI5, ACE5 and AHB5 protocols, which extend prior generations to include a number of performances and scalability features, to align and complement CHI.


The AMBA CHI (Coherent Hub Interface) specification defines the interfaces for the connection of fully coherent processors. For example, the Cortex-A76 and Cortex-A65, and dynamic memory controllers, such as the CoreLink DMC-620, to high performance, non-blocking interconnects, such as the CoreLink CMN-600. It is appropriate for a wide range of applications that require coherency, including mobile, networking, automotive, and data centers.

The AMBA CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area. This separation allows interconnect designs ranging from an efficient, small cross-bar to high performance, large scale mesh network.

AMBA CHI has been architected to maintain performance, as the number of components and quantity of traffic rises. This includes placing additional requirements on masters to respond to coherent snoop transactions, which means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.

The protocol also provides a Quality of Service (QoS) mechanism to control how resources in the system, shared by many processors, are allocated without needing a detailed understanding of every component and how they might interact.

Some of the key features include:

  • Support for high frequency, non-blocking coherent data transfer between many processors.
  • A layered model to allow separation of communication and transport protocols for flexible topologies, such as a cross-bar, ring, mesh or ad hoc.
  • Cache stashing to allow accelerators or IO devices to stash critical data within a CPU cache for low latency access.
  • Far atomic operations enable the interconnect to perform high-frequency updates to shared data.
  • End-to-end data protection and poisoning signaling.

The latest AMBA CHI specification details performance and transaction improvements, as well as new optional features, such as Memory partitioning (MPAM) and Interface parity protection.

AMBA CHI Specification


The AMBA AXI (Advanced eXtensible Interface) and ACE (AXI Coherency Extension) specification defines the protocols to implement high frequency, high bandwidth interconnect designs across a wide range of applications, including mobile, consumer, networking, automotive, and embedded. ACE5, ACE5-Lite, and AXI5 protocols extend prior generations, to include a number of performance and scalability features to align and complement AMBA CHI.

Some of the new features and options include:

  • Atomic transactions.
  • Cache stashing.
  • Data protection and poisoning signaling.
  • Armv8.1 Distributed Virtual Memory (DVM) messages.
  • Quality of Service Accept signaling.
  • Persistent Cache Maintenance Operations (CMO).
  • Cache de-allocation transactions.

AMBA AXI and ACE Specification


The AMBA AHB (Advanced High-performance Bus) specification defines an interface protocol most widely used with Cortex-M processors, for embedded designs and other low latency SoCs.

The AHB5 protocol builds upon the previous generation of AHB-Lite with two key goals:

  • It complements the Armv8-M architecture and extends the TrustZone security foundation from the processor to the entire system.
  • It provides consistency and alignment with the AMBA 4 AXI specification to:
    • Ease integration of Cortex-A and Cortex-M based systems in a SoC.
    • Allow a unified TrustZone security solution inclusive of AXI and AHB systems.

The new properties introduced in the specification are:

  • Secure/Non-secure signaling in address phase to indicate secure or non-secure transactions.
  • Extended memory types to support more complex systems.
  • Exclusive transfers that support semaphore-type operations.

The AHB5 provides further clarifications of AHB-Lite protocol properties, as they become more widely adopted:

  • Multiple slave select for area efficiency.
  • Single-copy and multi-copy atomicity enabling scaling to multiple cores.
  • User signaling allowing for user extensions and consistency with the AMBA 4 AXI specification.

AMBA AHB Specification


The AMBA CXS specification defines a credited, non-blocking streaming interface protocol, used in point-to-point packetized communications. It is optimized for the transport of CCIX packets between an on-chip interconnect and a PCIe controller. CXS is also optimized for wide interfaces, which enables passing packets to a high data rate external interface and merging of multiple packets into a single transfer.

AMBA CXS Specification


The AMBA Adaptive Traffic Profiles (AMBA ATP) is a synthetic traffic framework and is capable of modeling systems' masters and slaves high-level memory access behaviour in a concise, simple and portable way. Traffic Profiles can be used across multiple tools and design/verification environments to assist with the design and verification of complex SoCs. 

Among other use cases, they enable a simpler and faster simulation mechanism that is, at the same time, predictable and adaptive.

AMBA ATP Specification


The AMBA DTI (Distributed Translation Interface) specification aligns with the Arm System MMU architecture, to define a scalable, distributed messaging protocol for translation services. In an SMMU implementation, there are typically three components:

  • A Translation Control Unit (TCU) that performs the translation table walks.
  • A Translation Buffer Unit (TBU) that intercepts transactions in need of translation and can cache those translations to reduce transaction latency.
  • A PCI Express (PCIe) Root Complex that includes Address Translation Services (ATS). 

DTI is a point-to-point protocol where each channel consists of a link, a DTI master, and a DTI slave.  The specification outlines two different protocols between DTI masters and slaves:

  • DTI-TBU – Defines communication between a TBU master and a TCU slave.
  • DTI-ATS – Defines communication between a PCIe Root Complex and a TCU slave.

AMBA DTI Specification