A Generic Interrupt Controller (GIC) takes interrupts from peripherals, prioritizes them, and delivers them to the appropriate processor core. The Arm GIC architecture has two forms in general use with the A-profile that are also applicable to the R-profile:
- GICv2 is a memory mapped solution supporting up to eight processors.
- GICv3 offers support for much higher interrupt counts and larger numbers of processors. This version includes support for the System registers in Armv8-A and Armv8-R designs.
- GICv4 adds supports the direct injection of virtual interrupts.
The M-profile has its own NVIC interrupt controller as an integral part of the M-profile architecture.
The following diagram shows a GIC taking interrupts from n different peripherals, and distributing them to two different processors. The table summarizes the major releases of the GIC specification and the processors that they are typically used with.
|GIC versions||Key features||Typically used with|
|GICv1||Support for up to eight PEs
Support for up to 1020 interrupt IDs
Support for two Security states
|Arm Cortex-A5 MPCore
Arm Cortex-A9 MPCore
Arm Cortex-R5 MPCore
Arm Cortex-R7 MPCore
Arm Cortex-R8 MPCore
|GICv2||All key features of GICv1
Support for virtualization
|Arm Cortex-A7 MPCore
Arm Cortex-A15 MPCore
Arm Cortex-A17 MPCore
|GICv3||All key features of GICv2
Support for more than eight PEs
Support for message-signaled interrupts
Support for more than 1020 interrupt IDs
System register access to the CPU Interface registers
An enhanced security model that separates Secure and Non-secure Group 1 interrupts
|Arm Cortex-A3x MPCore
Arm Cortex-A5x MPCore
Arm Cortex-A7x MPCore
|GICv4||All key features of GICv3
Direct injection of virtual interrupts Arm Cortex-A3x MPCore
|Arm Cortex-A5x MPCore
Arm Cortex-A7x MPCore
Learn more about the GIC, the operation of a GICv3 compliant interrupt controller, and configuration for use in a bare metal environment in the Learn the architecture GIC guide:
Arm GIC IP
The GIC-600AE is software compatible with GIC-600 and has additional safety features targeting ASIL B to ASIL D systems including fault management unit for error detection and reporting. The CoreLink GIC-600AE is part of the Arm Safety Ready program.
The GIC-500 detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. GIC-500 is configurable up to 128 single-threaded cores and 960 shared interrupts.
The GIC-600 detects, manages, virtualizes and distributes interrupts for Armv8.0-A processors. GIC-600 is configurable up to 512 processor threads per chip, up to 16 chips and 960 shared interrupts.
The GIC-400 is a configurable interrupt controller that supports virtualization and that you can implement in single-processor or multiprocessor systems.