Arm Generic Interrupt Controller | Community

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New online training course - Arm GICv3/v4 Essentials

Arm announces a new online training topic, Arm GICv3/v4 Essential. The course brings the subject of Arm’s Generic Interrupt Controller (GIC) architecture specification to life.

2 years ago by Joel Eaton

Changing Exception Level and Security State with an Armv8-A Fixed Virtual P

In this blog we will discuss the architectural features of Exception level and Security state in more detail. You may find it easier to download the code

2 years ago by tmeduthie

Retargeting and Enabling Exceptions with an ELF Image

Retargeting semihosting procedures and enabling hardware interrupt based functionality to an embedded system running in an emulator

3 years ago by tmeduthie

PC meets Arm: Integrating PCIExpress into the Arm Server Architecture

There are some significant challenges assembling server SoCs for the infrastructure market with the latest PCIExpress gen4 capabilities, this blog provides a brief overview of the challenges which will be covered in more detail at the Arm Techcon…

3 years ago by Nick

Community Forums

Answered	Forum FAQs ARM Community	6208 views	0 replies	Started 3 months ago by Annie Cracknell: Back on the 8th! :)	Answer this
Suggested answer	what is the Instruction L1 TLB and L2 TLB size?	60 views	2 replies	Latest 8 hours ago by DANNYWW	Answer this
Suggested answer	BootROM for A78 ROM Memory AArch64 Embedded Linux Armv8-A application processor Cortex-A78	77 views	1 replies	Latest 19 hours ago by 42Bastian Schick	Answer this
Suggested answer	what is VIPT behaves as PIPT?	247 views	5 replies	Latest 23 hours ago by Zenon Xiu	Answer this
Answered	Setting breakpoints at runtime and stepping on the Cortex A53.	484 views	9 replies	Latest 7 days ago by Zenon Xiu	Answer this
Suggested answer	Self hosted debug on Cortex A53, setting up a breakpoint to cause an exception.	109 views	1 replies	Latest 7 days ago by KelvinInIdaho	Answer this

Answered	Forum FAQs Started 3 months ago by Annie Cracknell: Back on the 8th! :)	0 replies 6208 views
Suggested answer	what is the Instruction L1 TLB and L2 TLB size? Latest 8 hours ago by DANNYWW	2 replies 60 views
Suggested answer	BootROM for A78 Latest 19 hours ago by 42Bastian Schick	1 replies 77 views
Suggested answer	what is VIPT behaves as PIPT? Latest 23 hours ago by Zenon Xiu	5 replies 247 views
Answered	Setting breakpoints at runtime and stepping on the Cortex A53. Latest 7 days ago by Zenon Xiu	9 replies 484 views
Suggested answer	Self hosted debug on Cortex A53, setting up a breakpoint to cause an exception. Latest 7 days ago by KelvinInIdaho	1 replies 109 views