Configure exception routing

To keep things simple, this guide will specify that all exceptions are taken at the highest exception level, EL3.

A summary of the instructions and registers in the architecture will help you to understand this section of the guide. In addition, you must keep in mind some rules that exceptions obey:

  • An exception routed to a higher exception level cannot be masked, apart from EL0 to EL1 which can be masked with PSTATE.
  • An exception routed to a lower exception level is always masked.
  • An exception routed to the current exception level can be masked by PSTATE.

To configure exception routing, you need to perform the following tasks:

  • Configure the Secure Configuration Register, SCR_EL3, to enable exception routing to EL3.
  • Set the Vector Based Address Register, VBAR_EL3, to point to a vector table.
  • Disable masking (or ignoring) of exceptions at EL3 by PSTATE.

To do these things, add this code to startup.s:

// Configure SCR_EL3
// ------------------
MOV  w1, #0              // Initial value of register is unknown
ORR  w1, w1, #(1 << 3)   // Set EA bit (SError routed to EL3)
ORR  w1, w1, #(1 << 2)   // Set FIQ bit (FIQs routed to EL3)
ORR  w1, w1, #(1 << 1)   // Set IRQ bit (IRQs routed to EL3)
MSR  SCR_EL3, x1

// Install vector table
// ---------------------
.global vectors
LDR  x0, =vectors

// Clear interrupt masks
// ----------------------
MSR  DAIFClr, #0xF
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