Arm A-Profile Architecture Developments 2026

The Arm Instruction Set Architecture (ISA) is central to how hardware and software work together. The ISA defines the instructions that Arm-based hardware executes. It continues to evolve to meet modern demands in AI, machine learning, chiplet adoption, and security. Ongoing innovation across the Arm ISA ensures that the Arm compute platform remains performant, efficient, secure, and flexible for developers.

AI is also changing the workloads that future systems need to support. This shift from model-centric AI towards more complex intelligent systems places new demands on the underlying compute platform. These demands include greater efficiency and performance, as well as the ability to coordinate increasingly diverse workloads.

Each year, Arm publishes updates to the A-Profile architecture alongside full Instruction Set and System Register documentation. In 2026, the latest update is Armv9.8-A.

This year Arm is also publishing information on new Future Architecture Technologies. These features are being developed for currently unreleased versions of the Arm architecture. Arm provides the ecosystem with relevant information and specifications in advance. This helps developers prepare software support before these new technologies are implemented in hardware.

This forward-looking approach matters because architecture must anticipate where software and workloads are heading years before those demands become mainstream. This includes the increasingly heterogeneous and agentic AI systems now beginning to emerge.

We will now look at some of the new features we have added this year.

Conditional fault instructions

Memory-safe languages, such as Rust, are increasingly used across the Arm ecosystem. These languages provide many benefits, but they can also come with a cost. For example, the executed code might include added checks, such as on array bounds or for null pointers:

These checks can increase code size and branch frequency, which puts more pressure on branch prediction logic. The 2026 extensions introduce the Conditional Fault instructions, which are designed for use cases such as those described above.

These tailored instructions can reduce some of the increase in code size. Branch predictors can treat these specialist instructions differently to regular branches, reducing the pressure on branch predictors.

Scoping release operations

The ability for software to communicate intent more precisely becomes increasingly valuable as systems grow more complex. This allows hardware to optimize execution without imposing unnecessary work.A store-release instruction provides a one-way barrier that affects loads and stores that precede it in program order.

Consider the following example:

…
STR   x0, [slow perip.]	Earlier unrelated access
…
STR  <critical section>	Write payload, then set flag
STR  <critical section>
STLR [flag]
…

The programmer’s intent is that the STLR (Store release) instruction provides ordering to the two STR (store) instructions that write a payload before the flag is set. However, as the STLR applies to all earlier explicit loads and stores, it will also order the STR before the critical section.

The code will still function as intended, but over-ordering can reduce performance and efficiency. The 2026 extensions add new instructions that enable programmers to limit the scope of store-release operations and avoid over-ordering.

…
STR   x0, [slow perip.]	Earlier unrelated access
…
SLBND	Write payload, then set flag
STR  <critical section>
STR  <critical section>
SRLS
STLR [flag]
…

The SLBND (Scoped release boundary) and SRLS (Scope release) instructions define the boundaries of the region affected by the STLR. This enables programmers to express the intent of the code to the hardware and allow hardware to optimize safely.

Other enhancements in Armv9.8-A

Other enhancements introduced as part of the 2026 extensions include:

• Reporting of the granularity of single-copy atomic operations.
• Scalable Vector Extension (SVE) load and store operations with RCpc semantics.
• SVE permute operations on 128-bit elements.
• New reserved encoding space for future hint operations.

Future Architecture Technologies

The Future Architecture Technologies being shared in 2026 are:

Configurable contiguous region sizes

Efficient memory management is already vital to modern systems and will remain important as we evolve to support AI and agentic workloads. When managing virtual memory, larger mappings can improve performance, while smaller mappings are more efficient in terms of allocated memory. Software must balance these two considerations.

The Arm architecture already supports contiguous mappings. This allows software to express that a fixed number of translations are contiguous in both the virtual and physical, or intermediate physical, address spaces and use the same attributes. Processors can then cache translations for the contiguous region more efficiently. The work on anonymous folios in Linux, for example, has shown the potential benefit of using contiguous mappings.

Arm is taking this concept further with configurable contiguous regions. Configurable contiguous regions allow software to specify how many entries are contiguous. This gives management software greater flexibility and more opportunities to use contiguous mappings.

Other Future Architecture Technologies

Other Future Architecture Technologies include:

• Packet filtering with the Statistical Profiling Extension (SPE)
• Instructions to better support IEEE-754-2019.

Summary

These capabilities arrive as AI computing continues to evolve. Increasingly agentic systems will bring together models, memory, software, tools and specialized compute. Work might be distributed across cloud, edge, and physical devices. That makes system-level efficiency, flexibility, and heterogeneous computing increasingly important.

Arm architecture is designed to provide a common, efficient compute foundation as those workloads evolve. It enables CPUs to work alongside specialized compute while giving the ecosystem a consistent architectural foundation across a wide range of systems.

The 2026 extensions continue the evolution of Arm’s A-Profile architecture. They help software express intent more precisely, reduce unnecessary overhead, and prepare the ecosystem for future hardware capabilities. These updates include Conditional Fault instructions, scoped release operations, and new Future Architecture Technologies. Together, these updates reflect Arm’s ongoing commitment to enabling performant, efficient, secure, and scalable computing across a rapidly changing software landscape.

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