Add power control to the SoC
The PCK-600 Power Control Kit provides several components for creating a clock and power infrastructure for an SoC. Use the components shown in the following table to provide the infrastructure for your SoC:
|Low-Power Distributor Q-Channel (LPD-Q)||Distributes a Q-Channel from one Q-Channel controller to up to 32 Q-Channel devices. The LPD-Q allows the Q-Channel interfaces of the devices under control to be aggregated to a clock controller or a Power Policy Unit. This aggregation allows you to observe the current states and control the quiescent of the devices in relation to clock or power state.|
|Clock Controller (CLK-CTRL)||Provides high-level clock gating for devices in a clock domain that support Q-Channel Low-Power Interface (LPI) clock gating.|
|Power Policy Unit (PPU)||
A configurable and programmable P-Channel or Q-Channel power domain controller. For controlling domain power modes in co-ordination with device quiescence, the PPU provides:
The PPU works alongside a Power Control State Machine (PCSM). The PCSM is a technology-dependent state machine for the sequencing of power switch chains and retention controls, which can include RAM and register retention. The PCSM executes power mode changes under PPU direction. The interface between the PPU and the PCSM is a P-Channel.
Note: The Arm CoreLink PCK-600 Power Control Kit Release Note contains a complete list of all available components.
Connect the PPU through its APB interface to the APB4 PPC. Use the LPD-Q connect to other components whose power state the PPU must control.