Add the timers as peripherals
The CMSDK provides three timers that can be incorporated into an SoC as APB4 peripherals, as you can see in the following table:
|Timer||A 32-bit down-counter that generates an interrupt when the counter reaches 0|
|Dual-input timers||A module containing two programmable 32-bit or 16-bit down-counters that can generate interrupts when they reach 0. The timers can run in one of the following modes: free-running, periodic, and one-shot|
|Watchdog||A module containing a 32-bit down-counter that generates an interrupt, which is used for a reset event. The watchdog, when running, must be periodically reset to prevent it generating the reset event. If a core is locked-up, the watch dog times out and result in the watchdog resetting the core. This mechanism provides a way to recover from software crashes.|
Note: The Arm Cortex-M0/M0+ System Design Kit Release Note contains a complete list of all available components, including other APB components.
Like all APB peripherals in a TrustZone-based system, an APB4 TrustZone Peripheral Protection Controller controls the timers.
You can use all the timers in your system. We strongly recommend that you include at least two watchdog timers in your system. Map one watchdog to the Secure world and map the other watchdog to the Non-secure world. The Secure world watchdog timer can reset the system. However, the Non-secure world watchdog timer must normally not be allowed to reset the system directly. Instead, on a reset timeout, the Non-secure watchdog requests that the Secure world performs a system reset on its behalf. We also recommend that you include a dual timer, or two more individual timers. Use one of the timers as a Secure timer and the other as a Non-secure timer.
The previous figures assume that the APB peripherals are in a separate clock or power domain. For this reason, the controller is connected to the AHB5 Bus Matrix through an AHB5 to APB4 Asynchronous Bridge. The bridge is not mandatory for TrustZone and is not part of the filter.