How does the IP fit together?
This section of the guide focuses on how to fit together the pieces of IP that we discussed in What pieces of IP do I need to make a secure IoT device? The components that make up the CoreLink SIE-200 IP create the system interconnect. This interconnect allows signals and transactions to pass from the Cortex-M23 or Cortex-M33 processor to the peripherals in the system. These peripherals could be, for example, CryptoCell IP or Wi-Fi IP. This section uses theoretical knowledge from the Platform Security Architecture to take the first steps towards realizing that knowledge in an SoC.
Let's look at Arm IP components, and explore how to work with them when designing an SoC. Begin by downloading any of the following Arm IP that you currently have access to:
- Cortex-M23 with ETM or MTB
- CryptoCell-312 Security IP
- PL011 UART
- PL022 SPI Synchronous Serial Port
- Corstone-201 Foundation IP, which contains all the other Arm IP mentioned in this section
Note: All the above IP that is listed in the preceding list is supplied with Arm Flexible Access.
Downloading the IP gives you access to the documentation and the RTL. Generally, IP is supplied with the following documentation:
|Technical Overview||For subsystems only. Describes the elements that make up a subsystem and the software that is available to use on it.|
|Configuration and Integration Manual||
|Technical Reference Manual||Includes low-level functional descriptions of IP components and a programmer's guide that provides register descriptions, memory maps, and interrupt maps.|
Use this documentation to expand on the knowledge that is presented in the following sections of this guide.
Note: The top-level directories in the Corstone-201 package are named according to product code. The README.txt file contains a key for the product codes to help you navigate the package.