Arm TrustZone technology
TrustZone for Armv8-M is a Security Extension for the Armv8-M architecture. Before TrustZone was introduced, SoC integrators still had to ensure the authenticity of secure assets. Integrators often created physically segregated Secure and Non-secure worlds with controlled access between the two worlds.
TrustZone provides the segregation that is necessary to support confidentiality. Because TrustZone is already defined in the processor and system architecture, the implementation of TrustZone is at the hardware level. In other words, TrustZone facilitates hardware-supported isolation.
TrustZone works by enabling regions in memory to be marked as Secure or Non-secure, which gives a Secure and a Non-secure memory world within TrustZone. Data and instructions that are stored in the Secure memory world are marked as Secure. Data and instructions that are stored in the Non-secure world are marked as Non-secure.
On a processor that supports TrustZone, there are two separate processor states: Secure state and Non-secure state. Code running in the Secure state can execute Secure instructions, and can also access Secure and Non-secure data. When code is running in a Non-secure state, the code can only execute Non-secure instructions and access Non-secure data. The processor can transition from Secure state to Non-secure state and back again. Transitioning from Non-secure code execution to Secure code execution is a controlled process. It is not possible to branch from Non-secure code to code at a random Secure address.
Two types of unit are responsible for defining the memory regions:
- An Implementation Defined Attribution Unit (IDAU). These units are implemented externally to the processor during SoC integration and allows the security partitioning of the memory map to be hardwired at integration. This approach reduces hardware and software overheads that are involved when defining security mapping for memory regions. You can think of an IDAU as defining default regions.
- A Security Attribution Unit (SAU). Unlike an IDAU, you can define SAU regions at runtime using registers. This enables a SAU to override IDAU default regions.
For TrustZone to function, either an IDAU, or an IDAU and a SAU, is required in the processor implementation. Otherwise memory regions cannot be defined.
You can also partition each security world into further subregions using the Memory Protection Units (MPUs) within each world. One set of MPUs defines the regions within Secure memory, and the other MPU defines the regions within Non-secure memory. You can use the MPUs to create regions where the data is read-only, non-executable. An MPU also allows a processor in privileged mode to define the memory accessibility when next running in non-privileged, user application, mode. Effectively, the processor manages user applications by ensuring that the memory region of each application is protected against access by another application.
It is the responsibility of the software team to create secure firmware that carries out initialization tasks. If either the SAU or the MPUs are available, one of these tasks is to partition memory into suitable regions.
PSA Trusted Base System Architecture for M (TBSA-M) recommends that, where possible, the system integrator implements a TrustZone-based system. To meet this recommendation, you must, where applicable, make sure that the IP you choose can utilize TrustZone technology. This topic is explored further in The processor and The Advanced Microcontroller Bus Architecture components.
Bus components that are based on AMBA 5 can identify TrustZone transactions and differentiate between Secure and Non-secure transactions. This feature allows the Security state of each transaction to be propagated from the CPU to the interconnect. The transactions then pass on, with their Security state, to other components in the system that require security awareness. A security flag (NS) on the bus identifies Secure TrustZone transactions.
Note: TrustZone is optional in some IPs. Remember to enable TrustZone when configuring a piece of IP.