Overview The goals of a secure IoT device Security - How can I secure my device? Security - Platform Security Architecture Security - Arm TrustZone technology Security - CryptoCell and CryptoIsland technologies Security - Mitigating against physical attacks Security - Implementing additional security IP - What IP do I need to make a secure IoT device? IP - The processor IP - The AMBA components IP - The CryptoCell IP - Power control, timers, Wi-Fi, and display Build - How does the IP fit together? Build - Starting to develop an example TBSA-M system Build - Select AMBA components to link the IP together Build - Connect to RAM, ROM, and eFlash memory Build - Connect the CryptoCell-312 Build - Add power control to the SoC Build - Add the timers as peripherals Build - Add a theoretical Wi-Fi and display component Build - Integrate the IP into the SoC Build - Add your own registers for the SoC Build - Arm subsystems SSE-123 - Exploring the SSE-123 Example Subsystem SSE-123 - SSE-123 features SSE-123 - Working with the SSE-123 SSE-123 - SSE-123 timers SSE-123 - SSE-123 registers SSE-123 - Debugging with the SSE-123 SSE-123 - The SSE-123 I/O port SSE-123 - Ideas for extending the SSE-123 Related information Next steps
Debugging with the SSE-123
The SSE-123 Integration provides a JTAG interface and a trace port. This debug integration consists of the following IP:
- M23 Debug Access Port (DAP)
- M23 Trace Port Interface Unit (TPIU)
- SoC-400 Cross Trigger Interface (CTI)
- SoC-400 Timestamp Generator
The former two pieces of IP come from the Cortex-M23 IP download. The latter two pieces of IP come from the CoreSight SoC-400 IP, which is a solution for the debug and trace of complex SoCs. The following table describes these pieces of IP:
| IP | Description |
|---|---|
| Cortex-M23 DAP | Supports the JTAG interface and provides access to the core debug system |
| Cortex-M23 TPIU | Integrates with the Cortex-M23 ETM and supports instruction tracing |
| SoC-400 CTI | Allows events to be broadcast to other components. Events are signaled to the CTI through trigger inputs. Trigger outputs are used to signal events to other components. For example, in the SSE-123 Integration, the CTI triggers the system counter. |
| SoC-400 Timestamp Generator | Generates a debug timestamp value that provides a consistent view of time for multiple debug related IP blocks in an SoC. The Timestamp Generator is a necessary component when the system has enabled debugging with trace. |
If you want to have similar capabilities in your SoC, you can render the SSE-123 with the debug option enabled. Then you can examine the rendered RTL and integrate the IP into your own system.
Note: The SoC-400 IP is part of the Corstone-201 Foundation IP, which Arm Flexible Access supplies.