Ideas for extending the SSE-123
This section covers three ideas for extending and modifying the SSE-123:
- Replace the Cortex-M23 processor with a Cortex-M33 processor
- Add a CryptoCell-312 to the subsystem
- Add 32-bit timers to the subsystem
The SSE-200 Subsystem for Embedded is more advanced than the SSE-123. When making these extensions, we recommend using the SSE-200 as an example of how you can integrate the extra IP.
Note: The SSE-200 contains the SSE-123 and is part of the Corstone-201 Foundation IP, which Arm Flexible Access supplies.
Replace the Cortex-M23 processor with a Cortex-M33 processor
The processor explores whether to use a Cortex-M23 processor or a Cortex-M33 processor in your SoC. The conclusion was that a Cortex-M23 processor would meet the performance requirements of your secure IoT device SoC. However, the possibility that more performance might be required was also accepted.
The SSE-123 uses a Cortex-M23 processor, which mirrors the choice of processor made previously. However, if you need more performance, or you need an FPU or DSP, you could upgrade the processor to a Cortex-M33. The SSE-200 contains two Cortex-M33 processors. If both processors are included, the usual setup is to have one processor running the operating system. The other processor acts as a coprocessor running occasionally and much faster.
If you choose to replace the Coretx-M23 processor in the SSE-123 with a Cortex-M33 processor, start by rendering the SSE-200 and looking at the RTL produced. When comparing the SSE-200 RTL with RTL rendered for the SSE-123, look at how the Cortex-M33 and Cortex-M23 processors integrate with the other components. These RTL examples provide insight into replacing a Cortex-M23 processor with a Cortex-M33.
Note: Section A2.2 of the Arm CoreLink SSE-200 Subsystem for Embedded Configuration and Integration Manual describes the render options available for the SSE-200. The information includes the option for including or excluding either of the Cortex-M33 processors.
Add a CryptoCell to the subsystem
The CryptoCell section explores how using a CryptoCell-312 in your SoC complements Arm TrustZone and fortifies the security of the device. The SSE-123 does not include a CrytoCell-312. However, the SSE-200 provides an option to include a CryptoCell-312.
Figure 2-1: Top-level element interconnections of the Arm CoreLink SSE-200 Subsystem for Embedded Technical Overview shows the CryptoCell placed in its own domain. The figure also shows use of two AHB5 Access Control Gates to form the boundary between the CryptoCell domain and the main domain. The master interface on the AHB5 bus matrix also connects to the CryptoCell-312 through an AHB5 to APB4 asynchronous bridge. This bridge has a secondary function as an ACG.
If you want to add a CryptoCell-312 to the SSE-123, render the SSE-200 with the CryptoCell option enabled. The example RTL provides insight into adding the CryptoCell.
Note: If the CryptoCell is positioned in the same clock and power domains of the main bus matrix, you do not require an ACG between the CryptoCell and the bus matrix.
Add 32-bit timers to the SSE-123 Subsystem
Figure 2-1: Top-level element interconnections of the Arm CoreLink SSE-200 Subsystem for Embedded Technical Overview shows a system control element. This element features an always-on timer and a secure watchdog that run on a slow 32KHz clock. Both components come from the CMSDK.
SSE-123 timers explores the 64-bit timers that are employed in the SSE-123. If you require CMSDK timers, you can add them to the system. You might add these timers in a situation where you require more timers that have different clock inputs. However, be aware that these timers do not share a timestamp with the system timers already in the system.