Overview The goals of a secure IoT device Security - How can I secure my device? Security - Platform Security Architecture Security - Arm TrustZone technology Security - CryptoCell and CryptoIsland technologies Security - Mitigating against physical attacks Security - Implementing additional security IP - What IP do I need to make a secure IoT device? IP - The processor IP - The AMBA components IP - The CryptoCell IP - Power control, timers, Wi-Fi, and display Build - How does the IP fit together? Build - Starting to develop an example TBSA-M system Build - Select AMBA components to link the IP together Build - Connect to RAM, ROM, and eFlash memory Build - Connect the CryptoCell-312 Build - Add power control to the SoC Build - Add the timers as peripherals Build - Add a theoretical Wi-Fi and display component Build - Integrate the IP into the SoC Build - Add your own registers for the SoC Build - Arm subsystems SSE-123 - Exploring the SSE-123 Example Subsystem SSE-123 - SSE-123 features SSE-123 - Working with the SSE-123 SSE-123 - SSE-123 timers SSE-123 - SSE-123 registers SSE-123 - Debugging with the SSE-123 SSE-123 - The SSE-123 I/O port SSE-123 - Ideas for extending the SSE-123 Related information Next steps
SSE-123 registers
The SSE-123 allows run-time configuration through registers. If you use the SSE-123 as the basis of your own system, you could extend the registers. Use these registers to provide run-time control over any additional components that you add.
The SSE-123 Subsystem registers are defined in the SSE-123 Subsystem memory map. The register blocks that you can see in the following table are available:
| Register block | Description |
|---|---|
| Subsystem information | Provides software with system information including the system version and how the system is configured. |
| Subsystem control | Provides registers for power, clocks, resets, and other general system control. |
| Secure privilege control | Allows software to control security gating units, which relate to the Secure state of the system. These registers are Secure privilege access only. For example, one of the registers permits software to configure Secure privilege access permissions for APB peripherals. |
| Non-secure privilege control | Allows software to control security gating units, which relate to the Non-secure state of the system. For example, one of the registers permits software to configure Non-secure privilege access permissions for external APB peripherals. |
| System timers | Allows software to control the security access control of the subsystem timers. Both timers can be given privileged or non-privileged access. |
| Watchdog timers | Allows software to control whether the refresh frame of each watchdog has privileged or non-privileged access. |
| Power Policy Unit | Allows software to control the Power Policy Control Unit. |
| SRAM memory protection control | Allows software to control the SRAM MPC registers. |
| Cortex-M23 processor Private Peripheral Bus (PPB) | Allows software to control the Cortex-M23 PPB. |