Overview The goals of a secure IoT device Security - How can I secure my device? Security - Platform Security Architecture Security - Arm TrustZone technology Security - CryptoCell and CryptoIsland technologies Security - Mitigating against physical attacks Security - Implementing additional security IP - What IP do I need to make a secure IoT device? IP - The processor IP - The AMBA components IP - The CryptoCell IP - Power control, timers, Wi-Fi, and display Build - How does the IP fit together? Build - Starting to develop an example TBSA-M system Build - Select AMBA components to link the IP together Build - Connect to RAM, ROM, and eFlash memory Build - Connect the CryptoCell-312 Build - Add power control to the SoC Build - Add the timers as peripherals Build - Add a theoretical Wi-Fi and display component Build - Integrate the IP into the SoC Build - Add your own registers for the SoC Build - Arm subsystems SSE-123 - Exploring the SSE-123 Example Subsystem SSE-123 - SSE-123 features SSE-123 - Working with the SSE-123 SSE-123 - SSE-123 timers SSE-123 - SSE-123 registers SSE-123 - Debugging with the SSE-123 SSE-123 - The SSE-123 I/O port SSE-123 - Ideas for extending the SSE-123 Related information Next steps
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SSE-123 timers

The SSE-123 contains the following timers:

  • Two system timers. You can map, by software, one timer for Secure mode and one timer for Non-secure mode.
  • Two watchdog timers. You can map, by software, one watchdog for Secure mode and one watchdog for Non-secure mode.
  • A system counter. This unit provides the timestamp that is used by all watchdog timer and system timers.

The timestamp-based timers are 64-bit and were developed for the SSE-123 and future IoT subsystems. The timers from the CMSDK, which were covered in Add the timers as peripherals, are 32-bit and can also be added if necessary. The SSE-123 system and watchdog timers function in the same way as the watchdog that is described in Add the timers as peripherals. The only exception is that these timers all need a shared reference timestamp input from which to derive their time. The system counter is part of the SSE-123 Integration and provides a 64-bit timestamp value that compatible components across the SoC can share.

Note: More information on the SSE-123 counters is available in Appendix B of the Arm SSE-123 Example Subsystem Technical Reference Manual.

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