Smaller IP

This section of the guide covers the smaller pieces of IP in the system. Except for the BP140 AXI Internal Memory Interface, the IP in this section connects to the NIC-400 interconnect through an APB interface.

BP140 AXI Internal Memory Interface

This SoC includes SRAM and ROM. This memory is internal to the SoC and requires an appropriate controller. We chose two BP140 AXI Internal Memory Interfaces.

The BP140 is an internal memory interface that has:

  • An AXI slave interface.
  • A single-port memory interface that is configurable for SRAM and ROM.

Note: If you require TrustZone protection for Secure memory regions on the SRAM or ROM, place a BP141 TrustZone AXI Memory Interface between the CCI-500 and the BP140. The BP141 is also available in the Arm Flexible Access program.

PL011 UART Universal Asynchronous Receiver/Transmitter

When configuring the PL011 UART Universal Asynchronous Receiver/ Transmitter, you must choose the Baud rate, stop bits, parity bits, and data bits.

The PL011 has an APB slave interface that is used both for configuration and for reading and writing data.

The clock signal must be free running for the UART to operate. The signal must never be gated. If an APB bridge is used to connect to the UART, the clock to the bridge can only be gated if the UART is disabled.

PL061 General Purpose Input/Output

The PL061 General Purpose Input/Output has eight I/O pins that you can configure:

  • To be input or output
  • To generate interrupts using edge or level detection on inputs

You can read and write from each of the pins using APB access.

Dual timer

In this SoC, the dual timer is configured to consist of two programmable 32-bit down counters, which generate interrupts when they reach 0. Providing a dual timer allows you to use one timer as a Secure timer and one timer as a Non-secure timer. The timers can run in one of the following modes: free-running, periodic, and one-shot.

The dual timer provides an APB slave interface.

Note: The dual timer is a component from the Cortex-M0/M0+ System Design Kit (CMSDK). The CMSDK is part of the Corstone-201 Foundation IP.

Watchdog timers

In this SoC, there are two watchdog timers. Each watchdog consists of a 32-bit down counter that generates an interrupt, which is used for a reset event. The watchdog, when running, must be periodically reset to prevent it generating the reset event. If a core is locked up, the watchdog times out and results in the watchdog resetting the core. This mechanism provides a way to recover from software crashes.

One watchdog is mapped to the Secure world and the other watchdog is mapped to the Non-secure world. The Secure world watchdog timer can reset the system. However, the Non-secure world watchdog timer must normally not be allowed to reset the system directly. Instead, on a reset timeout, the Non-secure watchdog requests that the Secure world performs a system reset on its behalf.

The watchdog provides an APB slave interface.

Note: The watchdog timer is a component from the CMSDK. The CMSDK is part of the Corstone-201 Foundation IP.

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