This section contains a diagram showing how the different pieces of IP in the dual Cortex-A53 SoC connect to each other. The diagram also shows external connections to system masters and RAM.
The following pieces of IP are used in the preceding figure:
- Cortex-A53 processor
- Mali-G52 graphics processor
- CoreLink CCI-500 Cache Coherent Interconnect
- CoreLink NIC-400 Cache Coherent Interconnect
- CoreLink GIC-500 Generic Interrupt Controller
- CoreLink MMU-500 System Memory Management Unit
- CoreLink TZC-400 TrustZone Address Space Controller
- CoreLink ADB-400 AMBA Domain Bridge
- CoreSight SoC-400 Debug and Trace
- BP140 AXI Internal Memory Interface
- PL011 UART Universal Asynchronous Receiver/Transmitter
- PL061 General Purpose Input/Output
- Corstone-201 Foundation IP, which contains all the other Arm IP mentioned in this section
Note: The Arm Flexible Access program supplies all the IP in the preceding list.
The Configuration sections of this guide explore how the pieces of IP in this SoC are configured. The Connections sections of the guide explore how these IP are connected to each other.
Note: The sections in this guide that relate to connections assume that Q-Channel or P-Channel Low-Power Interfaces (LPIs) are available for each piece of IP. Clock and Power Management in an SoC explores LPIs in more detail.