Using a CCI-500 in the SoC

The SoC requires an interconnect from the CoreLink Cache Coherent Interconnect (CCI) family. These interconnects provide ACE interfaces that the Cortex-A53 and Mali-G52 must connect to. Because the CCI-400 only provides two ACE slave masters, a CCI-500 is required. 

The CoreLink CCI-500 provides:

  • Between one and four ACE slave interfaces
  • Between zero and six ACE-Lite slave interfaces
  • Between one and four AXI4 master memory interfaces
  • Between one and two AXI4 master system interfaces

In this SoC, the CoreLink CCI-500 is configured to have:

  • Four ACE slave interfaces
  • Two ACE-Lite slave interfaces
  • Four AXI4 master memory interfaces
  • Two AXI4 master system interfaces

Note: If you need more than two AXI4 master system interfaces, and striping is not enabled, you can use memory interfaces as system interfaces.


The following table shows the IP that CCI-500 interfaces connect to in this SoC:

 Interface Number Connection
ACE master 4 Connect to the Cortex-A53 clusters, through ADB-400s, and the Mail-G52
ACE-Lite slave
Connect to the MMU-500 and GIC-500. The GIC-500 AXI master interface can use an ACE-Lite interface. 
Memory AXI4 master  Connect to two BP140 memory controllers and two third-party RAM controllers, through a TCZ-400
System AXI4 master  Connect to the NIC-400

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