Overview The possibilities of a dual Cortex-A53 SoC with a Mali GPU System diagram Configuring and connecting the Cortex-A53 processors Configuring and connecting the Mali-G52 Using a CCI-500 in the SoC Using a NIC-400 in the SoC Configuring and connecting the GIC-500 Configuring and connecting the MMU-500 Configuring and connecting the TZC-400 Configuring and connecting the ADB-400 Using the SoC-400 to create a debug subsystem Smaller IP Clock and power management in an SoC Related information Next steps
Using a CCI-500 in the SoC
The SoC requires an interconnect from the CoreLink Cache Coherent Interconnect (CCI) family. These interconnects provide ACE interfaces that the Cortex-A53 and Mali-G52 must connect to. Because the CCI-400 only provides two ACE slave masters, a CCI-500 is required.
The CoreLink CCI-500 provides:
- Between one and four ACE slave interfaces
- Between zero and six ACE-Lite slave interfaces
- Between one and four AXI4 master memory interfaces
- Between one and two AXI4 master system interfaces
Configuration
In this SoC, the CoreLink CCI-500 is configured to have:
- Four ACE slave interfaces
- Two ACE-Lite slave interfaces
- Four AXI4 master memory interfaces
- Two AXI4 master system interfaces
Note: If you need more than two AXI4 master system interfaces, and striping is not enabled, you can use memory interfaces as system interfaces.
Connections
The following table shows the IP that CCI-500 interfaces connect to in this SoC:
| Interface | Number | Connection |
| ACE master | 4 | Connect to the Cortex-A53 clusters, through ADB-400s, and the Mail-G52 |
| ACE-Lite slave |
4 | Connect to the MMU-500 and GIC-500. The GIC-500 AXI master interface can use an ACE-Lite interface. |
| Memory AXI4 master | 4 | Connect to two BP140 memory controllers and two third-party RAM controllers, through a TCZ-400 |
| System AXI4 master | 1 | Connect to the NIC-400 |