Choosing the fab process
Running a PPA analysis requires that the analysis team chooses a fab process that could potentially realize the IP. There are three choices to make, all of which can have a large effect on the results of the PPA analysis:
- The fab itself. Processes with identical names can vary considerably from fab to fab. Choosing the fab is as important as choosing the process.
- The fab process. Fabs generally offer a range of processes from older, slower, budget processes to new faster cutting-edge processes.
- The fab process option. Process options are design by the fab to optimize for specific properties, for example performance or power.
Note: Unless specified otherwise, Arm PPA analysis data sets are for TSMC processes.
In this section, the significance of channel length, also called gate length, is explored in relation to processes. In addition to channel length, physical IP libraries specify other critical dimensions, which are discussed in Choosing the physical IP libraries.
Introduction to fab process nomenclature
Fab processes were historically named after the minimum channel length, for example 1µm, 250nm, 90nm, 32 nm, 22nm, or 10nm, that the process supported. The transistors in the cells span the channel. Smaller channel lengths result in faster performance, and therefore later processes have names which indicate a smaller minimum channel length. Older processes are named in micrometers and new processes are named in nanometers.
In modern processes, the minimum length of a channel no longer defines the name of the process. Instead, the name designates some other minimum feature size. However, what this feature size refers to varies from fab to fab, and therefore the drift between fabs regarding their processes has increased. Although channel length no longer defines the name of the process, process design rules still specify a minimal value for this critical dimension, even though it can now be a larger value than the process name. In some cases, a finite choice of channel length options is defined. Physical IP libraries that are designed for 40nm process and below incorporate different channel lengths including the minimum allowed.
Note: Arm PPA analysis data sets specify the channel length of the physical IP library with which the analysis is performed. When reviewing PPA analysis data, remember that within the same process, you might have the option to move to a smaller channel length. Doing so will increase performance but at the cost of increased use of static power.
An example of fab process options
This section looks at the options which TSMC, the largest dedicated independent fab in the world, offers for their 28nm process:
Table 5‑1 TSMC options
||High-performance computing plus
Imagine that the analysis team had settled on running a PPA analysis using the TSMC 28nm processes. They would now have to choose one of the process options above. In some cases, they might run more than one analysis, to give a broader view of what the IP could achieve in real situations.
Note: Many of the PPA analysis data sets for processor IP offered as part of the Arm Flexible Access program were, in fact, calculated using the TSMC 28nm process. Arm PPA analysis data always specifies the process option chosen, regardless of which process was used. When reviewing PPA analysis data, remember that simply switching to another process option may get you closer to the ideal SoC implementation for your project.
How physical IP libraries fit with fab processes
Fab processes define a set of design rules. Physical IP libraries are designed for a specific process, giving options while at the same time adhering to the design rules of the process. For example, Arm physical IP libraries designed for the TSMC 28nm process support channel lengths of 38nm and 32nm. Choosing the appropriate library allows the analysis team to exercise judgement regarding the channel-length critical dimension, while ensuring that the physical implementation is correct for the process. Choosing the physical IP libraries contains more information on the options presented by physical IP libraries.
What does post-shrink mean in relation to a fab process?
As mentioned in How physical IP libraries fit with fab processes, the industry moves forward to a new process about every two years. Between these full process nodes, advancements in lithography techniques allow fabs to develop what are called half nodes. The improvements in manufacturing allow the same circuit from a full node to occupy less silicon real estate than the preceding full node.
In these situations, the lengths and areas in the physical layout are considered pre-shrink. This means that the half-node optimizations have not yet been applied to the analysis. To calculate the area that the circuit will truly take up on silicon, optical shrink must be considered. Using the 28nm half-node as an example, the shrink from the preceding 32nm full node is 0.9. Consequently, all lengths in the physical layout are multiplied by 0.9 and all areas are multiplied by 0.81 (0.9 x 0.9). The shrink factor for a half-node is not always 0.9 and is decided upon by the fab.
Note: Arm PPA analysis data sets always present post-shrink area data if a half-node was chosen to perform the analysis.