Performing PPA analysis for a system

There is nothing greatly different in running a PPA analysis for an entire system, for example an SoC, rather than a single piece of IP. However, analyzing a system does add more complexity. A single piece of IP usually contains one or two clocks. However, a system will contain many clocks with different modes of operation, and the PPA analysis team must decide what frequencies to set the clocks to. In addition, to drive meaningful power optimizations, the team must understand the power story of the system, and how the individual IPs perform in the context of a complete system. Different parts of the system might also run at different operating voltages.

A team that is tasked with generating system PPA data will have to repeat the following steps when pieces of IP are reconfigured and new IPs are added in:

  1. Set up the input for the system. This process is usually more complicated than setting up the input for a single piece of IP.
  2. Derive the timing constraints across the entire system.
  3. Derive a representative floorplan.
  4. Profile the system. The team assesses the need to tune frequency targets, adjusts bus widths, and looks for opportunities to insert and remove IPs, for example register slicing and asynchronous crossing. In this step, the team is tackling the challenges of implementation while maintaining the performance requirements of the system.

By repeating the preceding steps, the team is making sure that the system is implementable at each stage in its development. With a large system, arriving at a complete, implemented system can take months, partly due to the length of time that it takes to validate larger PPA trial implementations. If the team is building from a preconfigured system, the process can be sped up. This is because the system will have been built with a fab process and floorplan in mind.

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