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rtual CPU interface register descriptions

This section describes only registers whose implementation is specific to the Cortex-A73 processor.

All other registers are described in the ARM® Generic Interrupt Controller Architecture Specification.

VM Active Priority Register

The GICV_APR0 characteristics are:

PurposeFor software compatibility, this register is present in the virtual CPU interface. However, in a virtualized system, it is not used when preserving and restoring state.
Usage constraintsReading the content of this register and then writing the same values must not change any state because there is no requirement to preserve and restore state during a powerdown.
ConfigurationsAvailable in all configurations.
AttributesGICV_APR0 is a 32-bit register.

The Cortex-A73 processor implements the GICV_APR0 as an alias of GICH_APR0.

VM CPU Interface Identification Register

The GICV_IIDR characteristics are:

PurposeProvides information about the implementer and revision of the virtual CPU interface.
Usage constraintsThere are no usage constraints.
ConfigurationsAvailable in all configurations.
AttributesGICV_IIDR is a 32-bit register.

The bit assignments for the VM CPU Interface Identification Register are identical to the corresponding register in the CPU interface, see CPU Interface Identification Register.

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