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AArch64 Generic Timer register summary

The following table shows the AArch64 Generic Timer registers.

Table 9-2 AArch64 Generic Timer registers

Name Reset Width Description
CNTKCTL_EL1 -a 32-bit

Counter-timer Kernel Control register

CNTFRQ_EL0 UNK 32-bit

Counter-timer Frequency register

CNTPCT_EL0 UNK 64-bit

Counter-timer Physical Count register

CNTVCT_EL0 UNK 64-bit Counter-timer Virtual Count register
CNTP_TVAL_EL0 UNK 32-bit

Counter-timer Physical Timer TimerValue register

CNTP_CTL_EL0

-b

32-bit Counter-timer Physical Timer Control register
CNTP_CVAL_EL0 UNK 64-bit Counter-timer Physical Timer CompareValue register
CNTV_TVAL_EL0 UNK 32-bit

Counter-timer Virtual Timer TimerValue register

CNTV_CTL_EL0 -b 32-bit

Counter-timer Virtual Timer Control register

CNTV_CVAL_EL0 UNK 64-bit Counter-timer Virtual Timer CompareValue register
CNTVOFF_EL2 UNK 64-bit

Counter-timer Virtual Offset register

CNTHCTL_EL2

-c

32-bit

Counter-timer Hypervisor Control register

CNTHP_TVAL_EL2 UNK 32-bit

Counter-timer Hypervisor Physical Timer TimerValue register

CNTHP_CTL_EL2 -b 32-bit Counter-timer Hypervisor Physical Timer Control register
CNTHP_CVAL_EL2 UNK 64-bit

Counter-timer Hypervisor Physical Timer CompareValue register

CNTPS_TVAL_EL1 UNK 32-bit

Counter-timer Physical Secure Timer TimerValue register

CNTPS_CTL_EL1 -b 32-bit

Counter-timer Physical Secure Timer Control register

CNTPS_CVAL_EL1 UNK 64-bit

Counter-timer Physical Secure Timer CompareValue register

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for information about these registers.

a

The reset value for bits[9:8, 2:0] is 0b00000.

b 

The reset value for bit[0] and bit[1] is 0.

c

The reset value for bit[2] is 0 and for bits[1:0] is 0b11.

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