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-mcpu

Enables code generation for a specific Arm® processor.

Syntax

To specify a target processor, use:

-mcpu=name

-mcpu=name[+[no]feature+…] (for architectures with optional extensions)

Where:

name

Specifies the processor.

To view a list of all supported processors for your target, use:

-mcpu=list

feature

Is an optional architecture feature that might be enabled or disabled by default depending on the architecture or processor.

Note

In general, if an architecture supports the optional feature, then this optional feature is enabled by default. To determine whether the optional feature is enabled, use fromelf ‑‑decode_build_attributes.

+feature enables the feature if it is disabled by default. +feature has no effect if the feature is already enabled by default.

+nofeature disables the feature if it is enabled by default. +nofeature has no effect if the feature is already disabled by default.

Use +feature or +nofeature to explicitly enable or disable an optional architecture feature.

For AArch64 targets you can specify one or more of the following features if the architecture supports it:

  • aes - Cryptographic extension. See Cryptographic extensions for more information.
  • crc - CRC extension.
  • crypto - Cryptographic extension. See Cryptographic extensions for more information.
  • dotprod - Enables the SDOT and UDOT instructions. Supported in the Armv8.2 and later Application profile architectures, and is optional in Armv8.2 and Armv8.3.
  • fp - Floating-point extension.
  • fp16 - Armv8.2-A half-precision floating-point extension.
  • profile - Armv8.2-A statistical profiling extension.
  • ras - Reliability, Availability, and Serviceability extension.
  • simd - Advanced SIMD extension.
  • rcpc - Release Consistent Processor Consistent extension. This extension applies to Armv8.2 and later Application profile architectures.
  • sha2 - Cryptographic extension. See Cryptographic extensions for more information.

For AArch32 targets, you can specify one or more of the following features if the architecture supports it:

  • crc - CRC extension for architectures Armv8 and above.
  • dotprod - Enables the VSDOT and VUDOT instructions. Supported in Armv8.2 and later Application profile architectures, and is optional in Armv8.2 and Armv8.3.
  • dsp - DSP extension for the Armv8‑M.mainline architecture.
  • fp16 - Armv8.2-A half-precision floating-point extension.
  • ras - Reliability, Availability, and Serviceability extension.

Note

For AArch32 targets, you can use -mfpu to specify the support for floating-point, Advanced SIMD, and cryptographic extensions.

Note

To write code that generates instructions for these extensions, use the intrinsics described in the Arm® C Language Extensions.

Usage

You can use -mcpu option to enable and disable specific architecture features.

To disable a feature, prefix with no, for example cortex-a57+nocrypto.

To enable or disable multiple features, chain multiple feature modifiers. For example, to enable CRC instructions and disable all other extensions:

armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57+nocrypto+nofp+nosimd+crc

If you specify conflicting feature modifiers with -mcpu, the rightmost feature is used. For example, the following command enables the floating-point extension:

armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57+nofp+fp

You can prevent the use of floating-point instructions or floating-point registers for AArch64 targets with the -mcpu=name+nofp+nosimd option. Subsequent use of floating-point data types in this mode is unsupported.

Note

There are no software floating-point libraries for AArch64 targets. When linking for AArch64 targets, armlink uses AArch64 libraries that contain floating-point and Advanced SIMD instructions and registers. This applies even if you compile the source with -mcpu=<name>+nofp+nosimd to prevent the compiler from using floating-point and Advanced SIMD instructions and registers. Therefore, there is no guarantee that the linked image for AArch64 targets is entirely free of floating-point and Advanced SIMD instructions and registers.

To prevent the use of floating-point and Advanced SIMD instructions and registers in images that are linked for AArch64 targets, re-implement the library functions or create your own library that does not use floating-point and Advanced SIMD instructions and registers.

Default

For AArch64 targets (--target=aarch64-arm-none-eabi), the compiler generates generic code for the Armv8‑A architecture in AArch64 state by default.

For AArch32 targets (--target=arm-arm-none-eabi) there is no default. You must specify either -march (to target an architecture) or -mcpu (to target a processor).

To see the default floating-point configuration for your processor:

  1. Compile with -mcpu=name -S to generate the assembler file.
  2. Open the assembler file and check that the value for the .fpu directive corresponds to one of the -mfpu options. No .fpu directive implies -mfpu=none.

Cryptographic extensions

The following table shows which algorithms the cryptographic features include for AArch64 state in the different versions of the Armv8‑A architecture:

Feature Armv8‑A Armv8.1-A Armv8.2-A Armv8.3-A Armv8.4-A
+crypto SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, SHA512, SHA3, AES, SM3, SM4
+sha2 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256 SHA1, SHA256
+aes AES AES AES AES AES
+sha2+aes SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES SHA1, SHA256, AES

Note

SHA512, SHA3, SM3, and SM4 are only available in AArch64 state in Armv8.4-A.

For AArch32 state in Armv8‑A and Armv8‑R, if you specify an -mfpu option that includes the cryptographic extension, then the cryptographic extension supports the AES, SHA1, and SHA256 algorithms.

Examples

To list the processors that target the AArch64 state:

armclang --target=aarch64-arm-none-eabi -mcpu=list

To target the AArch64 state of a Cortex®‑A57 processor:

armclang --target=aarch64-arm-none-eabi -mcpu=cortex-a57 test.c

To target the AArch32 state of a Cortex‑A53 processor, generating A32 instructions:

armclang --target=arm-arm-none-eabi -mcpu=cortex-a53 -marm test.c

To target the AArch32 state of a Cortex‑A53 processor, generating T32 instructions:

armclang --target=arm-arm-none-eabi -mcpu=cortex-a53 -mthumb test.c
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