The Current Program Status Register (CPSR) holds:
The APSR flags.
The processor mode.
The interrupt disable flags.
The instruction set state (A32 or T32).
The endianness state.
The execution state bits for the IT block.
The execution state bits control conditional execution in the IT block.
Only the APSR flags are accessible in all modes. ARM deprecates
MSR instruction to change the endianness bit
(E) of the CPSR, in any mode. Each exception level can have its
own endianness, but mixed endianness within an exception level is
SETEND instruction is deprecated in
A32 and T32 and has no equivalent in A64.
The execution state bits for the IT block (IT[1:0]) and the
T32 bit (T) can be accessed by
MRS only in Debug state.